Introduction to Hardware-Software Co-Design presents a number of issues of fundamental importance for the design of integrated hardware software products such as embedded, communication, and multimedia systems. This book is a comprehensive introduction to the fundamentals of hardware/software co-design. Co-design is still a new field but one which has substantially matured over the past few years. This book, written by leading international experts, covers all the major topics including: fundamental issues in co-design; hardware/software co-synthesis algorithms; prototyping and emulation; target architectures; compiler techniques; specification and verification; system-level specification. Special chapters describe in detail several leading-edge co-design systems including Cosyma, LYCOS, and Cosmos. Introduction to Hardware-Software Co-Design contains sufficient material for use by teachers and students in an advanced course of hardware/software co-design. It also contains extensive explanation of the fundamental concepts of the subject and the necessary background to bring practitioners up-to-date on this increasingly important topic.

I am honored and delighted to write the foreword to this very first book about SystemC. It is now an excellent time to summarize what SystemC really is and what it can be used for. The main message in the area of design in the 2001 International Te- nologyRoadmapfor Semiconductors (ITRS) isthat"cost ofdesign is the greatest threat to the continuation ofthe semiconductor roadmap. " This recent revision of the ITRS describes the major productivity improvements of the last few years as "small block reuse," "large block reuse ," and "IC implementation tools. " In order to continue to reduce design cost, the - quired future solutions will be "intelligent test benches" and "embedded system-level methodology. " As the new system-level specification and design language, SystemC - rectly contributes to these two solutions. These will have the biggest - pact on future design technology and will reduce system implementation cost. Ittook SystemC less than two years to emerge as the leader among the many new and well-discussed system-level designlanguages. Inmy op- ion, this is due to the fact that SystemC adopted object-oriented syst- level design-the most promising method already applied by the majority of firms during the last couple of years. Even before the introduction of SystemC, many system designers have attempted to develop executable specifications in C++. These executable functional specifications are then refined to the well-known transaction level, to model the communication of system-level processes.

As diverse as tomorrow's society constituent groups may be, they will share the common requirements that their life should become safer and healthier, offering higher levels of effectiveness, communication and personal freedom. The key common part to all potential solutions fulfilling these requirements is wearable embedded systems, with longer periods of autonomy, offering wider functionality, more communication possibilities and increased computational power. As electronic and information systems on the human body, their role is to collect relevant physiological information, and to interface between humans and local and/or global information systems. Within this context, there is an increasing need for applications in diverse fields, from health to rescue to sport and even remote activities in space, to have real-time access to vital signs and other behavioral parameters for personalized healthcare, rescue operation planning, etc. This book's coverage will span all scientific and technological areas that define wearable monitoring systems, including sensors, signal processing, energy, system integration, communications, and user interfaces. Six case studies will be used to illustrate the principles and practices introduced.

This book contains the revised contributions of 18 tutorial speakers at the seventh AACD '98 in Copenhagen, April 28-30, 1998. The conference was organized by OIe Olesen, ofthe Technical University of Denmark. The pro gram committee consisted of Johan H. Huijsing from Delft University ofTechnology, The Netherlands, Willy Samsen from the Katholieke Universiteit Leuven, Belgium and Rudy J. van de Plassche, Philips Research, The Netherlands. The pro gram was concentrated around three important topics in analog circuit design. Each of these three topics has been covered by six papers. Each of the three chapters of this book contains the six papers of one topic. The three topics are: I-Volt Electronics Design and implementation ofMixed Modes Systems. Low-Noise and RF power Amplifies for the communication. Other topics, which have been covered in this series before are: 1992 OpAmps ADC's AnalogCAD. 1993 Mixed-Mode AlD design Sensor Interfaces Communication circuits. 1994 Low-Power low-Voltage Integrated Filters Smart Power. 1995 Low-Noise, Low-Power, Low-Voltage Mixed Mode with CAD Tirals Voltage, Current and Time References. vii viii 1996 RF CMOS circuit design BandpassSigma Delta and other Converters Translinear circuits. 1997 RF A-D Converters Sensor and Actuator Interfaces Low-noise Oscillators, PLL's and and Synthesizers. We hope to serve the analog design community with these series of books and plan to continue this series in the future.

During the last few years Field Programmable Gate Arrays (FPGAs) have become increasingly important. Thanks to recent breakthroughs in technology, FPGAs offer millions of system gates at low cost and considerable speed. Functional decomposition has emerged as an essential technique in automatic logic synthesis for FPGAs. Functional decomposition as a technique to find realizations for Boolean functions was already introduced in the late fifties and early sixties by Ashenhurst, Curtis, Roth and Karp. In recent years, however, it has attracted a great deal of renewed attention, for several reasons. First, it is especially well suited for the synthesis of lookup-table based FPGAs. Also, the increased capacities of today's computers as well as the development of new methods have made the method applicable to larger-scale problems. Modern techniques for functional decomposition profit from the success of Reduced Ordered Binary Decision Diagrams (ROBDDs), data structures that provide compact representations for many Boolean functions occurring in practical applications. We have now seen the development of algorithms for functional decomposition which work directly based on ROBDDs, so that the decomposition algorithm works based on compact representations and not on function tables or decomposition matrices as in previous approaches. The book presents, in a consistent manner, a comprehensive presentation of a multitude of results stemming from the author's as well as various researchers' work in the field. Apart from the basic method, it also covers functional decomposition for incompletely specified functions, decomposition for multi-output functions and non-disjoint decomposition. Functional Decomposition with Application to FPGA Synthesis will be of interest both to researchers and advanced students in logic synthesis, VLSI CAD, and Design Automation as well as professionals working in FPGA design and the development of algorithms for FPGA synthesis.

This new book on Analog Circuit Design contains the revised contributions of all the tutorial speakers of the eight workshop AACD (Advances in Analog Circuit Design), which was held at Nice, France on March 23-25, 1999. The workshop was organized by Yves Leduc of TI Nice, France. The program committee consisted of Willy Sansen, K.U.Leuven, Belgium, Han Huijsing, T.U.Delft, The Netherlands and Rudy van de Plassche, T.U.Eindhoven, The Netherlands. The aim of these AACD workshops is to bring together a restricted group of about 100 people who are personally advancing the frontiers of analog circuit design to brainstorm on new possibilities and future developments in a restricted number of fields. They are concentrated around three topics. In each topic six speakers give a tutorial presentation. Eighteen papers are thus included in this book. The topics of 1999 are: (X)DSL and other communication systems RF MOST models Integrated filters and oscillators The other topics, which have been coverd before, are: 1992 Operational amplifiers A-D Converters Analog CAD 1993 Mixed-mode A]D design Sensor interfaces Communication circuits 1994 Low-power low-voltage design Integrated filters Smart power 1995 Low-noise low-power low-voltge design Mixed-mode design with CAD tools Voltage, current and time references vii viii 1996 RF CMOS circuit design Bandpass sigma-delta and other data converters Translinear circuits 1997 RF A-D Converters Sensor and actuator interfaces Low-noise oscillators, PLL's and synthesizers 1998 I-Volt electronics Design and implementation of mixed-mode systems Low-noise amplifiers and RF power amplifiers for telecommunications

Design reuse is not just a topic of research but a real industrial necessity in the microelectronic domain and thus driving the competitiveness of relevant areas like for example telecommunication or automotive. Most companies have already dedicated a department or a central unit that transfer design reuse into reality. All main EDA conferences include a track to the topic, and even specific conferences have been established in this area, both in the USA and in Europe. Virtual Components Design and Reuse presents a selection of articles giving a mature and consolidated perspective to design reuse from different points of view. The authors stem from all relevant areas: research and academia, IP providers, EDA vendors and industry. Some classical topics in design reuse, like specification and generation of components, IP retrieval and cataloguing or interface customisation, are revisited and discussed in depth. Moreover, new hot topics are presented, among them IP quality, platform-based reuse, software IP, IP security, business models for design reuse, and major initiatives like the MEDEA EDA Roadmap.

A critical step in the design of a DSP system is to identify for each of its components (DSP kernels) an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. The book covers the entire solution space comprising both hardware multiplier-based and multiplex-less architectures that offer varying degrees of programmability. For each of the implementation styles, several algorithmic and architectural transformations are proposed so as to optimally implement weighted-sum based DSP kernels over the area-display-power space. VLSI Synthesis of DSP Kernels presents the following: Six different target implementation styles - Programmable DSP-based implementation; Programmable processors with no dedicated hardware multiplier; Implementation using hardware multiplier(s) and adder(s); Distributed Arithmetic (DA)-based implementation; Residue Number System (RNS)-based implementation; and Multiplier-less implementation (using adders and shifters) for fixed coefficient DSP kernels. For each of the implementation styles, description and analysis of several algorithmic and architectural transformations aimed at one or more of reduced area, higher performance and low power; Automated and semi-automated techniques for applying each of these transformations; and Classification of the transformations based on the properties that they exploit and their encapsulation in a design framework. A methodology that uses the framework to systematically explore the application of these transformations depending on the characteristics of the algorithm and the target implementation style. VLSI Synthesis of DSP Kernels is essential reading for designers of both hardware- and software-based DSP systems, developers of IP modules for DSP applications, EDA tools developers, researchers and managers interested in getting a comprehensive overview of current trends and future challenges in optimal implementations of DSP kernels. It will also be suitable for graduate students specialising in the area of VLSI Digital Signal Processing.

The design of computer systems to be embedded in critical real-time applications is a complex task. Such systems must not only guarantee to meet hard real-time deadlines imposed by their physical environment, they must guarantee to do so dependably, despite both physical faults (in hardware) and design faults (in hardware or software). A fault-tolerance approach is mandatory for these guarantees to be commensurate with the safety and reliability requirements of many life- and mission-critical applications. This book explains the motivations and the results of a collaborative project', whose objective was to significantly decrease the lifecycle costs of such fault tolerant systems. The end-user companies participating in this project already deploy fault-tolerant systems in critical railway, space and nuclear-propulsion applications. However, these are proprietary systems whose architectures have been tailored to meet domain-specific requirements. This has led to very costly, inflexible, and often hardware-intensive solutions that, by the time they are developed, validated and certified for use in the field, can already be out-of-date in terms of their underlying hardware and software technology."

This book aims at providing a view of the current trends in the development of research on Synthesis and Control of Discrete Event Systems. Papers col lected in this volume are based on a selection of talks given in June and July 2001 at two independent meetings: the Workshop on Synthesis of Concurrent Systems, held in Newcastle upon Tyne as a satellite event of ICATPN/ICACSD and organized by Ph. Darondeau and L. Lavagno, and the Symposium on the Supervisory Control of Discrete Event Systems (SCODES), held in Paris as a satellite event of CAV and organized by B. Caillaud and X. Xie. Synthesis is a generic term that covers all procedures aiming to construct from specifications given as input objects matching these specifications. The ories and applications of synthesis have been studied and developped for long in connection with logics, programming, automata, discrete event systems, and hardware circuits. Logics and programming are outside the scope of this book, whose focus is on Discrete Event Systems and Supervisory Control. The stress today in this field is on a better applicability of theories and algorithms to prac tical systems design. Coping with decentralization or distribution and caring for an efficient realization of the synthesized systems or controllers are of the utmost importance in areas so diverse as the supervision of embedded or man ufacturing systems, or the implementation of protocols in software or in hard ware."

Computer-Aided Innovation (CAI) is emerging as a strategic domain of research and application to support enterprises throughout the overall innovation process. The 5.4 Working Group of IFIP aims at defining the scientific foundation of Computer Aided Innovation systems and at identifying state of the art and trends of CAI tools and methods. These Proceedings derive from the second Topical Session on Computer- Aided Innovation organized within the 20th World Computer Congress of IFIP. The goal of the Topical Session is to provide a survey of existing technologies and research activities in the field and to identify opportunities of integration of CAI with other PLM systems. According to the heterogeneous needs of innovation-related activities, the papers published in this volume are characterized by multidisciplinary contents and complementary perspectives and scopes. Such a richness of topics and disciplines will certainly contribute to the promotion of fruitful new collaborations and synergies within the IFIP community. Gaetano Cascini th Florence, April 30 20 08 CAI Topical Session Organization The IFIP Topical Session on Computer-Aided Innovation (CAI) is a co-located conference organized under the auspices of the IFIP World Computer Congress (WCC) 2008 in Milano, Italy Gaetano Cascini CAI Program Committee Chair [email protected]

Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from the first principles.

Also treated are the resulting effects so the reader understands the effectiveness of leakage power reduction solutions under these different conditions.

Case studies supply real-world examples that reap the benefits of leakage power reduction solutions as the book highlights different device design choices that exist to mitigate increases in the leakage components as technology scales.

In recent years meshless/meshfree methods have gained considerable attention in engineering and applied mathematics. The variety of problems that are now being addressed by these techniques continues to expand and the quality of the results obtained demonstrates the effectiveness of many of the methods currently available. The book presents a significant sample of the state of the art in the field with methods that have reached a certain level of maturity while also addressing many open issues. The book collects extended original contributions presented at the Second ECCOMAS Conference on Meshless Methods held in 2007 in Porto. The list of contributors reveals a fortunate mix of highly distinguished authors as well as quite young but very active and promising researchers, thus giving the reader an interesting and updated view of different meshless approximation methods and their range of applications. The material presented is appropriate for researchers, engineers, physicists, applied mathematicians and graduate students interested in this active research area.

Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to perform research that leads to advances in the design and development of more efficient, effective, and elegant algorithms and design tools. Organization of the Book The book is organized as follows. A multi-stage simulated annealing algorithm that integrates floorplanning and interconnect planning is pre sented in Chapter 1. To reduce the run time, different interconnect plan ning approaches are applied in different ranges of temperatures. Chapter 2 introduces a new design methodology - the interconnect-centric design methodology and its centerpiece, interconnect planning, which consists of physical hierarchy generation, floorplanning with interconnect planning, and interconnect architecture planning. Chapter 3 investigates a net-cut minimization based placement tool, Dragon, which integrates the state of the art partitioning and placement techniques."

The application of geometric algebra to the engineering sciences is a young, active subject of research. The promise of this field is that the mathematical structure of geometric algebra together with its descriptive power will result in intuitive and more robust algorithms.

This book examines all aspects essential for a successful application of geometric algebra: the theoretical foundations, the representation of geometric constraints, and the numerical estimation from uncertain data. Formally, the book consists of two parts: theoretical foundations and applications. The first part includes chapters on random variables in geometric algebra, linear estimation methods that incorporate the uncertainty of algebraic elements, and the representation of geometry in Euclidean, projective, conformal and conic space. The second part is dedicated to applications of geometric algebra, which include uncertain geometry and transformations, a generalized camera model, and pose estimation.

Graduate students, scientists, researchers and practitioners will benefit from this book. The examples given in the text are mostly recent research results, so practitioners can see how to apply geometric algebra to real tasks, while researchers note starting points for future investigations. Students will profit from the detailed introduction to geometric algebra, while the text is supported by the author's visualization software, CLUCalc, freely available online, and a website that includes downloadable exercises, slides and tutorials.

Design for Manufacturability and Statistical Design: A Comprehensive Approach presents a comprehensive overview of methods that need to be mastered in understanding state-of-the-art design for manufacturability and statistical design methodologies. Broadly, design for manufacturability is a set of techniques that attempt to fix the systematic sources of variability, such as those due to photolithography and CMP. Statistical design, on the other hand, deals with the random sources of variability. Both paradigms operate within a common framework, and their joint comprehensive treatment is one of the objectives of this book and an important differentation.

This book covers in a great depth the fast growing topic of tools, techniques and applications of soft computing (e.g., fuzzy logic, genetic algorithms, neural networks, rough sets, Bayesian networks, and other probabilistic techniques) in the ontologies and the Semantic Web. The author shows how components of the Semantic Web (like the RDF, Description Logics, ontologies) can be covered with a soft computing methodology.

Here is a textbook for senior undergraduate and graduate level students that offers a novel and systematic look into the dynamics of MEMS. It includes numerous solved examples together with the proposed problems. The material to be found here will also be of interest to researchers with a non-mechanical background. The book focuses on the mechanical domain, specifically the dynamic sub-domain, and provides an in-depth treatment of problems that involve reliable modeling, analysis and design.

Design for Manufacturability and Yield for Nano-Scale CMOS walks the reader through all the aspects of manufacturability and yield in a nano-CMOS process and how to address each aspect at the proper design step starting with the design and layout of standard cells and how to yield-grade libraries for critical area and lithography artifacts through place and route, CMP model based simulation and dummy-fill insertion, mask planning, simulation and manufacturing, and through statistical design and statistical timing closure of the design. It alerts the designer to the pitfalls to watch for and to the good practices that can enhance a design s manufacturability and yield. This book is a must read book the serious practicing IC designer and an excellent primer for any graduate student intent on having a career in IC design or in EDA tool development."

At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.

In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.

Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user s existing verification environment, in other words the testbench infrastructure.

The guiding principles promoted in this book when creating an assertion-based IP monitor are:

• modularity assertion-based IP should have a clear separation between detection and action
  
• clarity assertion-based IP should be written initially focusing on capturing intent (versus optimizations)

A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers.

From the Foreword:

Creating Assertion-Based IP " reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP This book will serve as a valuable reference for years to come."
Andrew Piziali, Sr. Design Verification Engineer
Co-Author, ESL Design and Verification: A Prescription for Electronic System Level Methodology
Author, Functional Verification Coverage Measurement and Analysis"

This edited volume is targeted at presenting the latest state-of-the-art methodologies in "Hybrid Evolutionary Algorithms." The chapters deal with the theoretical and methodological aspects, as well as various applications to many real world problems from science, technology, business or commerce. Overall, the book has 14 chapters including an introductory chapter giving the fundamental definitions and some important research challenges. The contributions were selected on the basis of fundamental ideas/concepts rather than the thoroughness of techniques deployed.

This book deals with the analysis and design of CMOS current-mode circuits for data communications. CMOS current-mode sampled-data networks, i.e. switched-current circuits, are excluded. Major subjects covered in the book include: a critical comparison of voltage-mode and current-mode circuits; the building blocks of current-mode circuits: design techniques; modeling of wire channels, electrical signaling for Gbps data communications; ESD protection for current-mode circuits and more. This book will appeal to IC design engineers, hardware system engineers and others.

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.