Logic Synthesis and Optimization presents up-to-date research information in a pedagogical form. The authors are recognized as the leading experts on the subject. The focus of the book is on logic minimization and includes such topics as two-level minimization, multi-level minimization, application of binary decision diagrams, delay optimization, asynchronous circuits, spectral method for logic design, field programmable gate array (FPGA) design, EXOR logic synthesis and technology mapping. Examples and illustrations are included so that each contribution can be read independently. Logic Synthesis and Optimization is an indispensable reference for academic researchers as well as professional CAD engineers.

Switching Theory for Logic Synthesis covers the basic topics of switching theory and logic synthesis in fourteen chapters. Chapters 1 through 5 provide the mathematical foundation. Chapters 6 through 8 include an introduction to sequential circuits, optimization of sequential machines and asynchronous sequential circuits. Chapters 9 through 14 are the main feature of the book. These chapters introduce and explain various topics that make up the subject of logic synthesis: multi-valued input two-valued output function, logic design for PLDs/FPGAs, EXOR-based design, and complexity theories of logic networks. An appendix providing a history of switching theory is included. The reference list consists of over four hundred entries. Switching Theory for Logic Synthesis is based on the author's lectures at Kyushu Institute of Technology as well as seminars for CAD engineers from various Japanese technology companies. Switching Theory for Logic Synthesis will be of interest to CAD professionals and students at the advanced level. It is also useful as a textbook, as each chapter contains examples, illustrations, and exercises.

The Background to the Institute The NATO Advanced Study Institute (ASI) 'People and Computers - Applying an Anthropocentric Approach to Integrated Production Systems and Organisations' came about after the distribution of a NATO fact sheet to BruneI University, which described the funding of ASls. The 'embryonic' director of the ASI brought this opportunity to the attention of the group of people, (some at BruneI and some from outside), who were together responsible for the teaching and management of the course in Computer Integrated Manufacturing (CIM) in BruneI's Department of Manufacturing and Engineering Systems. This course had been conceived in 1986 and was envisaged as a vehicle for teaching manufacturing engineering students the technology of information integration through project work. While the original idea of the course had also included the organisational aspects of CIM, the human factors questions were not considered. This shortcoming was recognised and the trial run of the course in 1988 contained some lectures on 'people' issues. The course team were therefore well prepared and keen to explore the People, Organisation and Technology (POT) aspects of computer integration, as applied to industrial production. A context was proposed which would allow the inclusion of people from many different backgrounds and which would open up time and space for reflection. The proposal to organise a NATO ASI was therefore welcomed by all concerned.

A Formal Approach to Hardware Design discusses designing computations to be realised by application specific hardware. It introduces a formal design approach based on a high-level design language called Synchronized Transitions. The models created using Synchronized Transitions enable the designer to perform different kinds of analysis and verification based on descriptions in a single language. It is, for example, possible to use exactly the same design description both for mechanically supported verification and synthesis. Synchronized Transitions is supported by a collection of public domain CAD tools. These tools can be used with the book in presenting a course on the subject. A Formal Approach to Hardware Design illustrates the benefits to be gained from adopting such techniques, but it does so without assuming prior knowledge of formal design methods. The book is thus not only an excellent reference, it is also suitable for use by students and practitioners.

One of the main applications of VHDL is the synthesis of electronic circuits. Circuit Synthesis with VHDL is an introduction to the use of VHDL logic (RTL) synthesis tools in circuit design. The modeling styles proposed are independent of specific market tools and focus on constructs widely recognized as synthesizable by synthesis tools. A statement of the prerequisites for synthesis is followed by a short introduction to the VHDL concepts used in synthesis. Circuit Synthesis with VHDL presents two possible approaches to synthesis: the first starts with VHDL features and derives hardware counterparts; the second starts from a given hardware component and derives several description styles. The book also describes how to introduce the synthesis design cycle into existing design methodologies and the standard synthesis environment. Circuit Synthesis with VHDL concludes with a case study providing a realistic example of the design flow from behavioral description down to the synthesized level. Circuit Synthesis with VHDL is essential reading for all students, researchers, design engineers and managers working with VHDL in a synthesis environment.

Testing techniques for VLSI circuits are undergoing many exciting changes. The predominant method for testing digital circuits consists of applying a set of input stimuli to the IC and monitoring the logic levels at primary outputs. If, for one or more inputs, there is a discrepancy between the observed output and the expected output then the IC is declared to be defective. A new approach to testing digital circuits, which has come to be known as IDDQ testing, has been actively researched for the last fifteen years. In IDDQ testing, the steady state supply current, rather than the logic levels at the primary outputs, is monitored. Years of research suggests that IDDQ testing can significantly improve the quality and reliability of fabricated circuits. This has prompted many semiconductor manufacturers to adopt this testing technique, among them Philips Semiconductors, Ford Microelectronics, Intel, Texas Instruments, LSI Logic, Hewlett-Packard, SUN microsystems, Alcatel, and SGS Thomson. This increase in the use of IDDQ testing should be of interest to three groups of individuals associated with the IC business: Product Managers and Test Engineers, CAD Tool Vendors and Circuit Designers. Introduction to IDDQ Testing is designed to educate this community. The authors have summarized in one volume the main findings of more than fifteen years of research in this area.

The combination of VLSI process technology and real-time digital signal processing (DSP) has brought a break-through in information technology. This rapid technical (r)evolution allows the integration of ever more complex systems on a single chip. However, these technology and integration advances have not been matched by an increase in design productivity, causing technology to leapfrog the design of integrated circuits (ICs). The success of these emerging 'systems-on-a-chip' (SOC) can only be guaranteed by a systematic and formal design methodology, possibly automated in computer-aided design (CAD) tools, and effective re-use of existing intellectual property (IP). In this book, a contribution is made to the modeling, timing verification and analysis, and the automatic synthesis of integrated real-time DSP systems. Existing literature in these three domains is extensively reviewed, making this book the first to give a comprehensive overview of existing techniques.The emphasis throughout the book is on the support and guaranteeing of the real-time aspect and constraints of these systems, which avoids time consuming design iterations and safeguards the ever shrinking time-to-market. The proposed 'Multi-Thread Graph' (MTG) system model features two-layers, unifying a (timed) Petri net and a control-data flow graph. Its unique interface between both models offers the best of two worlds and introduces an extra abstraction level hiding the operation-level details which are unnecessary during global system exploration. The formulated timing analysis and verification approach supports the calculation of temporal separation between different MTG entities as well as realistic performance metrics for highly concurrent systems. The synthesis methodology focuses on managing the task-level concurrency (i.e. task scheduling), as part of a proposed overall system design meta flow. It emphasizes performance and timing aspects ('timeliness'), while minimizing processor cost overhead as driven by high-level cost estimators.The approach is new in the abstraction level it employs, and in its optimal hybrid dynamic/static scheduling policy which, driven by cost estimators, selects the scheduling policy for each behavior. At the low-level, RTOS synthesis generates an application-specific scheduler for the software component. The proposed synthesis methodology (at the task-level) is asserted to yield most optimal results when employed before the hardware/software partition is made. At this level, the distinction between these two is minimal, such that all steps in the design trajectory can be shared, thereby reducing the system cost significantly and allowing tighter satisfaction of timing/performance constraints. From the Foreword: This book is the first comprehensive treatment of software, and more general, system, generation (synthesis) techniques based on formal models. It can be used as a very valuable reference to understand the development of the field of embedded software design, and of system design and synthesis in general. The book offers an invaluable help to researchers and practitioners of the field of embedded system design. Prof. Alberto Sangiovanni-Vincentelli, Edgar L. and Harold H.Buttner Professor of Electrical Engineering and Computer Science, University of California, Berkeley, Chief Technology Advisor, Cadence Design Systems.

Oversampling techniques based on sigma-delta modulation are widely used to implement the analog/digital interfaces in CMOS VLSI technologies. This approach is relatively insensitive to imperfections in the manufacturing process and offers numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in the low-voltage environment that is increasingly demanded by advanced VLSI technologies and by portable electronic systems. In The Design of Low-Voltage, Low-Power Sigma-Delta Modulators, an analysis of power dissipation in sigma-delta modulators is presented, and a low-voltage implementation of a digital-audio performance A/D converter based on the results of this analysis is described. Although significant power savings can typically be achieved in digital circuits by reducing the power supply voltage, the power dissipation in analog circuits actually tends to increase with decreasing supply voltages. Oversampling architectures are a potentially power-efficient means of implementing high-resolution A/D converters because they reduce the number and complexity of the analog circuits in comparison with Nyquist-rate converters. In fact, it is shown that the power dissipation of a sigma-delta modulator can approach that of a single integrator with the resolution and bandwidth required for a given application. In this research the influence of various parameters on the power dissipation of the modulator has been evaluated and strategies for the design of a power-efficient implementation have been identified. The Design of Low-Voltage, Low-Power Sigma-Delta Modulators begins with an overview of A/D conversion, emphasizing sigma-delta modulators. It includes a detailed analysis of noise in sigma-delta modulators, analyzes power dissipation in integrator circuits, and addresses practical issues in the circuit design and testing of a high-resolution modulator. The Design of Low-Voltage, Low-Power Sigma-Delta Modulators will be of interest to practicing engineers and researchers in the areas of mixed-signal and analog integrated circuit design.

Application-Driven Architecture Synthesis describes the state of the art of architectural synthesis for complex real-time processing. In order to deal with the stringent timing requirements and the intricacies of complex real-time signal and data processing, target architecture styles and target application domains have been adopted to make the synthesis approach feasible. These approaches are also heavily application-driven, which is illustrated by many realistic demonstrations, used as examples in the book. The focus is on domains where application-specific solutions are attractive, such as significant parts of audio, telecom, instrumentation, speech, robotics, medical and automotive processing, image and video processing, TV, multi-media, radar, sonar. Application-Driven Architecture Synthesis is of interest to both academics and senior design engineers and CAD managers in industry. It provides an excellent overview of what capabilities to expect from future practical design tools, and includes an extensive bibliography.

The intense drive for signal integrity has been at the forefront of rapid and new developments in CAD algorithms. With increasing demands for high signal speeds coupled with a decrease in feature size, interconnect effects such as signal delay, distortion and crosstalk become the dominant factor limiting overall performance of VLSI systems. Although SPICE is used on a daily basis by many engineers for analog simulation and general circuit analysis, current versions of SPICE do not handle adequately the new emerging challenges of interconnect effects. Moment-matching techniques, such as asymptotic waveform evaluation, have recently proven useful in the analysis of large interconnect structures containing elements such as lossy coupled transmission lines with linear or nonlinear terminations. At a CPU cost of a little more than one DC analysis, these techniques are 2--3 orders of magnitude faster than full simulation techniques such as FFT. Asymptotic Waveform Evaluation presents an overview of the diverse algorithms and applications of moment matching techniques. The material is presented systematically and is supported by many examples.Issues such as sensitivity analysis and three-dimensional analysis are also covered. Asymptotic Waveform Evaluation will be of interest to engineers, students and researchers involved in the development and study of circuit simulation as well as interconnect analysis. It will also interest design engineers who are involved in dealing with high-speed issues, and graduate students who are active in the development of CAD tools for electronic systems.

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout. Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.

This book presents a detailed summary of research on automatic layout of device-level analog circuits that was undertaken in the late 1980s and early 1990s at Carnegie Mellon University. We focus on the work behind the creation of the tools called KOAN and ANAGRAM II, which form part of the core of the CMU ACACIA analog CAD system. KOAN is a device placer for custom analog cells; ANANGRAM II a detailed area router for these analog cells. We strive to present the motivations behind the architecture of these tools, including detailed discussion of the subtle technology and circuit concerns that must be addressed in any successful analog or mixed-signal layout tool. Our approach in organizing the chapters of the book has been to present our algo rithms as a series of responses to these very real and very difficult analog layout problems. Finally, we present numerous examples of results generated by our algorithms. This research was supported in part by the Semiconductor Research Corpora tion, by the National Science Foundation, by Harris Semiconductor, and by the International Business Machines Corporation Resident Study Program. Finally, just for the record: John Cohn was the designer of the KOAN placer; David Garrod was the designer of the ANAGRAM II router (and its predeces sor, ANAGRAM I). This book was architected by all four authors, edited by John Cohn and Rob Rutenbar, and produced in finished form by John Cohn.

As MOS devices are scaled to meet increasingly demanding circuit specifications, process variations have a greater effect on the reliability of circuit performance. For this reason, statistical techniques are required to design integrated circuits with maximum yield. Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits describes a statistical circuit simulation and optimization environment for VLSI circuit designers. The first step toward accomplishing statistical circuit design and optimization is the development of an accurate CAD tool capable of performing statistical simulation. This tool must be based on a statistical model which comprehends the effect of device and circuit characteristics, such as device size, bias, and circuit layout, which are under the control of the circuit designer on the variability of circuit performance. The distinctive feature of the CAD tool described in this book is its ability to accurately model and simulate the effect in both intra- and inter-die process variability on analog/digital circuits, accounting for the effects of the aforementioned device and circuit characteristics. Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits serves as an excellent reference for those working in the field, and may be used as the text for an advanced course on the subject.

Physical Design for Multichip Modules collects together a large body of important research work that has been conducted in recent years in the area of Multichip Module (MCM) design. The material consists of a survey of published results as well as original work by the authors. All major aspects of MCM physical design are discussed, including interconnect analysis and modeling, system partitioning and placement, and multilayer routing. For readers unfamiliar with MCMs, this book presents an overview of the different MCM technologies available today. An in-depth discussion of various recent approaches to interconnect analysis are also presented. Remaining chapters discuss the problems of partitioning, placement, and multilayer routing, with an emphasis on timing performance. For the first time, data from a wide range of sources is integrated to present a clear picture of a new, challenging and very important research area. For students and researchers looking for interesting research topics, open problems and suggestions for further research are clearly stated.Points of interest include: * Clear overview of MCM technology and its relationship to physical design; * Emphasis on performance-driven design, with a chapter devoted to recent techniques for rapid performance analysis and modeling of MCM interconnects; * Different approaches to multilayer MCM routing collected together and compared for the first time; * Explanation of algorithms is not overly mathematical, yet is detailed enough to give readers a clear understanding of the approach; * Quantitative data provided wherever possible for comparison of different approaches; * A comprehensive list of references to recent literature on MCMs provided.

Synthesis of Finite State Machines: Logic Optimization is the second in a set of two monographs devoted to the synthesis of Finite State Machines (FSMs). The first volume, Synthesis of Finite State Machines: Functional Optimization, addresses functional optimization, whereas this one addresses logic optimization. The result of functional optimization is a symbolic description of an FSM which represents a sequential function chosen from a collection of permissible candidates. Logic optimization is the body of techniques for converting a symbolic description of an FSM into a hardware implementation. The mapping of a given symbolic representation into a two-valued logic implementation is called state encoding (or state assignment) and it impacts heavily area, speed, testability and power consumption of the realized circuit. The first part of the book introduces the relevant background, presents results previously scattered in the literature on the computational complexity of encoding problems, and surveys in depth old and new approaches to encoding in logic synthesis. The second part of the book presents two main results about symbolic minimization; a new procedure to find minimal two-level symbolic covers, under face, dominance and disjunctive constraints, and a unified frame to check encodability of encoding constraints and find codes of minimum length that satisfy them. The third part of the book introduces generalized prime implicants (GPIs), which are the counterpart, in symbolic minimization of two-level logic, to prime implicants in two-valued two-level minimization. GPIs enable the design of an exact procedure for two-level symbolic minimization, based on a covering step which is complicated by the need to guarantee encodability of the final cover. A new efficient algorithm to verify encodability of a selected cover is presented. If a cover is not encodable, it is shown how to augment it minimally until an encodable superset of GPIs is determined. To handle encodability the authors have extended the frame to satisfy encoding constraints presented in the second part. The covering problems generated in the minimization of GPIs tend to be very large. Recently large covering problems have been attacked successfully by representing the covering table with binary decision diagrams (BDD). In the fourth part of the book the authors introduce such techniques and extend them to the case of the implicit minimization of GPIs, where the encodability and augmentation steps are also performed implicitly. Synthesis of Finite State Machines: Logic Optimization will be of interest to researchers and professional engineers who work in the area of computer-aided design of integrated circuits.

For many years, the dominant fault model in automatic test pattern gen eration (ATPG) for digital integrated circuits has been the stuck-at fault model. The static nature of stuck-at fault testing when compared to the extremely dynamic nature of integrated circuit (IC) technology has caused many to question whether or not stuck-at fault based testing is still viable. Attempts at answering this question have not been wholly satisfying due to a lack of true quantification, statistical significance, and/or high computational expense. In this monograph we introduce a methodology to address the ques tion in a manner which circumvents the drawbacks of previous approaches. The method is based on symbolic Boolean functional analyses using Or dered Binary Decision Diagrams (OBDDs). OBDDs have been conjectured to be an attractive representation form for Boolean functions, although cases ex ist for which their complexity is guaranteed to grow exponentially with input cardinality. Classes of Boolean functions which exploit the efficiencies inherent in OBDDs to a very great extent are examined in Chapter 7. Exact equa tions giving their OBDD sizes are derived, whereas until very recently only size bounds have been available. These size equations suggest that straight forward applications of OBDDs to design and test related problems may not prove as fruitful as was once thought."

Field-Programmable Gate Arrays (FPGAs) have emerged as an attractive means of implementing logic circuits, providing instant manufacturing turnaround and negligible prototype costs. They hold the promise of replacing much of the VLSI market now held by mask-programmed gate arrays. FPGAs offer an affordable solution for customized VLSI, over a wide variety of applications, and have also opened up new possibilities in designing reconfigurable digital systems. Field-Programmable Gate Arrays discusses the most important aspects of FPGAs in a textbook manner. It provides the reader with a focused view of the key issues, using a consistent notation and style of presentation. It provides detailed descriptions of commercially available FPGAs and an in-depth treatment of the FPGA architecture and CAD issues that are the subjects of current research. The material presented is of interest to a variety of readers, including those who are not familiar with FPGA technology, but wish to be introduced to it, as well as those who already have an understanding of FPGAs, but who are interested in learning about the research directions that are of current interest.

In the design of any visual objects, the work becomes much easier if previous designs are utilized. Computer graphics is becoming increasingly important simply because it greatly helps in utilizing such previous designs. Here, "previous designs" signifies both design results and design procedures. The objects designed are diverse. For engineers, these objects could be machines or electronic circuits, as discussed in Chap. 3, ''CA~/CAM. '' Physicians often design models of a patient's organs from computed tomography images prior to surgery or to assist in diagnosis. This is the subject of Chap. 8, "Medical Graphics. " Chapter 7, "Computer Art," deals with the way in which artists use computer graphics in creating beautiful visual images. In Chap. 1, "Computational Geometry," a firm basis is provided for the definition of shapes in designed objects; this is a typical technical area in which computer graphics is constantly making worldwide progress. Thus, the present volume, reflecting international advances in these and other areas of computer graphics, provides every potential or actual graphics user with the essential up-to-date information. There are, typically, two ways of gathering this current information. One way is to invite international authorities to write on their areas of specialization. Usually this works very well if the areas are sufficiently established that it is possible to judge exactly who knows what. Since computer graphics, however, is still in its developmental stage, this method cannot be applied.

This volume is about automation - automation in design, automation in manufacturing, and automation in production. Automation is essen tial for increased productivity of quality products at reduced costs. That even partial or piecemeal automation of a production facility can deliver dramatic improvements in productivity has been amply demon strated in many a real-life situation. Hence, currently, great ef forts are being devoted to research and development of general as well special methodologies of and tools for automation. This volume re ports on some of these methodologies and tools. In general terms, methodologies for automation can be divided into two groups. There are situations where a process, whether open-loop or closed-loop, is fairly clearly understood. In such a situation, it is possible to create a mathematical model and to prescribe a mathe matical procedure to optimize the output. If such mathematical models and procedures are computationally tractable, we call the correspond ing automation - algorithmic or parametric programming. There is, however, a second set of situations which include process es that are not well understood and the available mathematical models are only approximate and discrete. While there are others for which mathematical procedures are so complex and disjoint that they are computationally intractable. These are the situations for which heuristics are quite suitable for automation. We choose to call such automation, knowledge-based automation or heuristic programming."

This text addresses the design methodologies and CAD tools available for the systematic design and design automation of analogue integrated circuits. Two complementary approaches discussed increase analogue design productivity, demonstrated throughout using design times of the different design experiments undertaken.

It is now a decade since the appearance of W. Diffie and M. E. Hellmann's startling paper, "New Directions in Cryptography." This paper not only established the new field of public-key cryptography but also awakened scientific interest in secret-key cryptography, a field that had been the almost exclusive domain of secret agencies and mathematical hobbyist. A number of ex cellent books on the science of cryptography have appeared since 1976. In the main, these books thoroughly treat both public-key systems and block ciphers (i. e. secret-key ciphers with no memo ry in the enciphering transformation) but give short shrift to stream ciphers (i. e., secret-key ciphers wi th memory in the enciphering transformation). Yet, stream ciphers, such as those . implemented by rotor machines, have played a dominant role in past cryptographic practice, and, as far as I can determine, re main still the workhorses of commercial, military and diplomatic secrecy systems. My own research interest in stream ciphers found a natural re sonance in one of my doctoral students at the Swiss Federal Institute of Technology in Zurich, Rainer A. Rueppe1. As Rainer was completing his dissertation in late 1984, the question arose as to where he should publish the many new results on stream ciphers that had sprung from his research."

This book constitutes the refereed proceedings of the European Design Science Symposium, EDSS 2011, held in Leixlip, Ireland, in October 2011 held in conjunction with the Intel European Research and Innovation Conference, ERIC 2011. The 15 revised full papers presented were carefully reviewed and selected from various submissions. The papers are organized in topical sections on design science and processes; evaluation and utility; and applying design science.

This book constitutes the refereed proceedings of the 9th International Conference on Cooperative Design, Visualization, and Engineering, CDVE 2012, held in Osaka, Japan, in September 2012. The 36 revised full papers presented were carefully reviewed and selected from numerous submissions. The papers cover the topics of cooperative engineering, basic theories, methods and technologies that support CDVE, cooperative design, visualization and applications.

The total integration of the process of designing, manufacturing, and supporting a product from the earliest conceptual phase to the time it is removed from service remains an unfulfilled dream. Yet, when we look at the enormity of the process of integration even for the most simply conceived and manufactured items, we can recognize that substantial progress has been and is being made. It is our nature to be dissatisfied with near term progress, but when we realize how short a time the tools to do that integration have been available, the progress is clearly noteworthy - considering the multitudes of subjects we have to deal with. Most of the integration problems we confront today are multidisciplinary in nature. They require not only the knowledge and experience in a variety of fields but also good cooperation from different disciplined organizations to adequately comprehend and solve such problems. In Volume I we have many examples that reflect the current state of the art in integration of engineer ing and production processes. The papers for Volume I have been arranged in a more or less logical order of conceptual. design, computer-based modeling, analysis, production, and manufacturing. Chapter I is devoted to those with a design and geometrie modeling emphasis; Chapter II is devoted to an engineering analysis emphasis; and Chapter III to a production/manufacturing emphasis."

Knighting in sequence biology Edward N. Trifonov Genome classification, construction of phylogenetic trees, became today a major approach in studying evolutionary relatedness of various species in their vast - versity. Although the modern genome clustering delivers the trees which are very similar to those generated by classical means, and basic terminology is the same, the phenotypic traits and habitats are not anymore the playground for the classi- cation. The sequence space is the playground now. The phenotypic traits are - placed by sequence characteristics, "words", in particular. Matter-of-factually, the phenotype and genotype merged, to confusion of both classical and modern p- logeneticists. Accordingly, a completely new vocabulary of stringology, information theory and applied mathematics took over. And a new brand of scientists emerged - those who do know the math and, simultaneously, (do?) know biology. The book is written by the authors of this new brand. There is no way to test their literacy in biology, as no biologist by training would even try to enter into the elite circle of those who masters their almost occult language. But the army of - formaticians, formal linguists, mathematicians humbly (or aggressively) longing to join modern biology, got an excellent introduction to the field of genome cl- tering, written by the team of their kin.