Embedded systems are informally defined as a collection of programmable parts surrounded by ASICs and other standard components, that interact continuously with an environment through sensors and actuators. The programmable parts include micro-controllers and Digital Signal Processors (DSPs). Embedded systems are often used in life-critical situations, where reliability and safety are more important criteria than performance. Today, embedded systems are designed with an ad hoc approach that is heavily based on earlier experience with similar products and on manual design. Use of higher-level languages such as C helps structure the design somewhat, but with increasing complexity it is not sufficient. Formal verification and automatic synthesis of implementations are the surest ways to guarantee safety. Thus, the POLIS system which is a co-design environment for embedded systems is based on a formal model of computation. POLIS was initiated in 1988 as a research project at the University of California at Berkeley and, over the years, grew into a full design methodology with a software system supporting it. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach is intended to give a complete overview of the POLIS system including its formal and algorithmic aspects. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach will be of interest to embedded system designers (automotive electronics, consumer electronics and telecommunications), micro-controller designers, CAD developers and students.

The modern wireless communication industry has put great demands on circuit designers for smaller, cheaper transceivers in the gigahertz frequency range. One tool which has assisted designers in satisfying these requirements is the use of on-chip inductiveelements (inductors and transformers) in silicon (Si) radio-frequency (RF) integrated circuits (ICs). These elements allow greatly improved levels of performance in Si monolithic low-noise amplifiers, power amplifiers, up-conversion and down-conversion mixers and local oscillators. Inductors can be used to improve the intermodulation distortion performance and noise figure of small-signal amplifiers and mixers. In addition, the gain of amplifier stages can be enhanced and the realization of low-cost on-chip local oscillators with good phase noise characteristics is made feasible. In order to reap these benefits, it is essential that the IC designer be able to predict and optimize the characteristics of on-chip inductiveelements. Accurate knowledge of inductance values, quality factor (Q) and the influence of ad- cent elements (on-chip proximity effects) and substrate losses is essential. In this book the analysis, modeling and application of on-chip inductive elements is considered. Using analyses based on Maxwells equations, an accurate and efficient technique is developed to model these elements over a wide frequency range. Energy loss to the conductive substrate is modeled through several mechanisms, including electrically induced displacement and conductive c- rents and by magnetically induced eddy currents. These techniques have been compiled in a user-friendly software tool ASITIC (Analysis and Simulation of Inductors and Transformers for Integrated Circuits).

Physicians, lawyers, engineers, architects, financial analysts, and other pro fessionals articulate an increasing need for support by intelligent workstations for decision making, analysis, communication, and other activities. "Intelligent Workstations for Professionals" is the collection of papers presented by inter national scientists at a symposium and workshop in March 1992. Requirements from potential users, studies of their behavior as well as approaches and aspects oftechnical realizations of "intelligent" functions are introduced. Eight contributions from members of the Center for Information and Tele communication Technology (Clrn of Northwestern University, Wisconsin Whitewater University, and the Children's Memorial Hospital deal with the latest findings of the UNIS (Users' Needs for Intelligent Systems) project, which is designed to identify needs and wishes from professionals for intelligent sup port systems and the potential barriers to adoption and use of such systems. The remaining papers concentrate on new approaches and techniques that en hance the "intelligence" of future workstations. They tackle issues like architectural trends in workstation design, the combination of workstations with HDTV and speech processing, automatic reading and understanding of documents, the automated development of software, or the processing of in exact knowledge. These papers were contributed by members of the DFKI GmbH (German Research Institute for Artificial Intelligence), GMD mbH (German Society for Mathematics and Data Processing), Siemens Gammasonics Inc., Siemens Nixdorf Informationssysteme AG and Siemens AG."

Design and Analysis of Distributed Embedded Systems is organized similar to the conference. Chapters 1 and 2 deal with specification methods and their analysis while Chapter 6 concentrates on timing and performance analysis. Chapter 3 describes approaches to system verification at different levels of abstraction. Chapter 4 deals with fault tolerance and detection. Middleware and software reuse aspects are treated in Chapter 5. Chapters 7 and 8 concentrate on the distribution related topics such as partitioning, scheduling and communication. The book closes with a chapter on design methods and frameworks.

Designing is one of the most significant of human acts. Surprisingly, given that designing has been occurring for many millenia, our understanding of the processes of designing is remarkably limited. Recently, design methods have been formalised not as humano-centred processes but as processes capable of computer implementation with the goal of augmenting human designers. This volume contains contributions which cover design methods based on evolutionary systems, generative processes, evaluation methods and analysis methods. It presents the state of the art in formal design methods for computer aided design.

INTRODUCTION TO COMPUTER-AIDED DESIGN OF USER INTERFACES l 2 Jean Vanderdonckt and Angel Puerta ,3 Jlnstitut d'Administration et de Gestion - Universite catholique de Louvain Place des Doyens, 1 - B-1348 Louvain-la-Neuve (Belgium) vanderdonckt@gant,ucl. ac,be , vanderdoncktj@acm,org Web: http://www. arpuerta. com JKnowledge Systems Laboratory, Stanford University, MSOB x215 Stanford, CA 94305-5479, USA puena@camis. stanford. edu 3RedWhaie Corp. , 277 Town & Country Village Palo Alto, CA 94303, USA puerta@ redwhale. com Web: http://www. redwhale. com Computer-Aided Design of Vser Interfaces (CADUI) is hereby referred to as the particular area of Human-Computer Interaction (HCI) intended to provide software support for any activity involved in the development life cycle of an interactive application, Such activities namely include task analysis, contextual inquiry [l], requirements definition, user-centred design, application modelling, conceptual design, prototyping, programming, in- stallation, test, evaluation, maintenance, Although very recently addressed (e. g. , [3]), the activity of re-designing an existing user interface (VI) for an interactive application and the activity of re-engineering a VI to rebuild its underlying models are also considered in CADVI. A fundamental aim of CADVI is not only to provide some software sup- port to the above activities, but also to incorporate strong and solid meth- odological aspects into the development, thus fostering abstraction reflection and leaving ad hoc development aside [5,7]. Incorporating such methodo- logical aspects inevitably covers three related, sometimes intertwined, facets: models, method and tools.

Many different kinds of FPGAs exist, with different programming technologies, different architectures and different software. Field-Programmable Gate Array Technology describes the major FPGA architectures available today, covering the three programming technologies that are in use and the major architectures built on those programming technologies. The reader is introduced to concepts relevant to the entire field of FPGAs using popular devices as examples. Field-Programmable Gate Array Technology includes discussions of FPGA integrated circuit manufacturing, circuit design and logic design. It describes the way logic and interconnect are implemented in various kinds of FPGAs. It covers particular problems with design for FPGAs and future possibilities for new architectures and software. This book compares CAD for FPGAs with CAD for traditional gate arrays. It describes algorithms for placement, routing and optimization of FPGAs. Field-Programmable Gate Array Technology describes all aspects of FPGA design and development. For this reason, it covers a significant amount of material. Each section is clearly explained to readers who are assumed to have general technical expertise in digital design and design tools. Potential developers of FPGAs will benefit primarily from the FPGA architecture and software discussion. Electronics systems designers and ASIC users will find a background to different types of FPGAs and applications of their use.

xv From the Old to the New xvii Acknowledgments xxi 1 Verilog - A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs.

This book presents a new set of embedded system design techniques called multidimensional data flow, which combine the various benefits offered by existing methodologies such as block-based system design, high-level simulation, system analysis and polyhedral optimization. It describes a novel architecture for efficient and flexible high-speed communication in hardware that can be used both in manual and automatic system design and that offers various design alternatives, balancing achievable throughput with required hardware size. This book demonstrates multidimensional data flow by showing its potential for modeling, analysis, and synthesis of complex image processing applications. These applications are presented in terms of their fundamental properties and resulting design constraints. Coverage includes a discussion of how far the latter can be met better by multidimensional data flow than alternative approaches. Based on these results, the book explains the principles of fine-grained system level analysis and high-speed communication synthesis. Additionally, an extensive review of related techniques is given in order to show their relation to multidimensional data flow.

Future computer aided design systems will themselves be designed using tools and methods that are still under development. This book presents the latest progress in research on the tools and methods needed to develop those CAD systems. The topics covered include algorithmic aspects, the product data and development process, future CAD architectures, feature based modeling and automatic feature recognition, complex surface design, and system implementation issues. The book contains contributions by the world's leading experts in the field of CAD technology from both universities and industry. The contributions are based on lectures given at the International Conference and Research Center for Computer Science, Schloss Dagstuhl, Germany.

As robots improve in efficiency and intelligence, there is a growing need to develop more efficient, accurate and powerful sensors in accordance with the tasks to be robotized. This has led to a great increase in the study and development of different kinds of sensor devices and perception systems over the last ten years. Applications that differ from the industrial ones are often more demanding in sensorics since the environment is not usually so well structured. Spatial and agricultural applications are examples of situations where the environment is unknown or variable. Therefore, the work to be done by a robot cannot be strictly programmed and there must be an interactive communication with the environment. It cannot be denied that evolution and development in robotics are closely related to the advances made in sensorics. The first vision and force sensors utilizing discrete components resulted in a very low resolution and poor accuracy. However, progress in VLSI, imaging devices and other technologies have led to the development of more efficient sensor and perception systems which are able to supply the necessary data to robots.

Based on the highly successful second edition, this extended edition of "SystemVerilog for Verification: A Guide to Learning the Testbench Language Features" teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill.

In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students' understanding of the material. Other features of this revision include: New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standardDescriptions of UVM features such as factories, the test registry, and the configuration databaseExpanded code samples and explanations Numerous samples that have been tested on the major SystemVerilog simulators

"SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition "is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.
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TOOLS Eastern Europe 2002 was the third annual conference on the technology of object-oriented languages and systems. It was held in Eastern Europe, more specifically in Sofia, Bulgaria, from March 13 to 15. In my capacity of program chairman, I could count on the support from the Programming Technology Lab of the Vrije Universiteit Brussel to set up the technical program for this con- ference. We managed to assemble a first class international program committee composed of the following researchers: * Mehmet Aksit (Technische Hogeschool Twente, Netherlands) * Jan Bosch (Universiteit Groningen, Netherlands) * Gilad Bracha (Sun Microsystems, USA) * Shigeru Chiba (Tokyo Institute of Technology, Japan) * Pierre Cointe (Ecole des Mines de Nantes, France) * Serge Demeyer (Universitaire Instelling Antwerpen, Belgium) * Pavel Hruby (Navision, Denmark) * Mehdi Jazayeri (Technische Universitiit Wien, Austria) * Eric Jul (University of Copenhagen, Denmark) * Gerti Kappel (University of Linz, Austria) * Boris Magnusson (University of Lund, Sweden) * Daniela Mehandjiiska-Stavreva (Bond University, Australia) * Tom Mens (Vrije Universiteit Brussel, Belgium) * Christine Mingins (Monash University, Australia) * Ana Moreira (Universidade Nova de Lisboa, Portugal) * Oscar Nierstrasz (Universitiit Bern, Switzerland) * Walter Olthoff (DFKI, Germany) * Igor Pottosin (A. P. Ershov Institute of Informatics Systems, Russia) * Atanas Radenski (Winston-Salem State University, USA) Markku Sakkinen (University of Jyvilskyl!l. , Finland) * * Bran Selic (Rational, Canada) * Andrey Terehov (St.

System-on-Chip for Real-Time Applications will be of interest to engineers, both in industry and academia, working in the area of SoC VLSI design and application. It will also be useful to graduate and undergraduate students in electrical and computer engineering and computer science. A selected set of papers from the 2nd International Workshop on Real-Time Applications were used to form the basis of this book. It is organized into the following chapters: -Introduction; -Design Reuse; -Modeling; -Architecture; -Design Techniques; -Memory; -Circuits; -Low Power; -Interconnect and Technology; -MEMS. System-on-Chip for Real-Time Applications contains many signal processing applications and will be of particular interest to those working in that community.

The Verilog Programming Language Interface, commonly called the Verilog PU, is one of the more powerful features of Verilog. The PU provides a means for both hardware designers and software engineers to interface their own programs to commercial Verilog simulators. Through this interface, a Verilog simulator can be customized to perform virtually any engineering task desired. Just a few of the common uses of the PU include interfacing Veri log simulations to C language models, adding custom graphical tools to a simulator, reading and writing proprietary file formats from within a simulation, performing test coverage analysis during simulation, and so forth. The applications possible with the Verilog PLI are endless. Intended audience: this book is written for digital design engineers with a background in the Verilog Hardware Description Language and a fundamental knowledge of the C programming language. It is expected that the reader: Has a basic knowledge of hardware engineering, specifically digital design of ASIC and FPGA technologies. Is familiar with the Verilog Hardware Description Language (HDL), and can write models of hardware circuits in Verilog, can write simulation test fixtures in Verilog, and can run at least one Verilog logic simulator. Knows basic C-language programming, including the use of functions, pointers, structures and file I/O. Explanations of the concepts and terminology of digital

The existence of electrical noise is basically due to the fact that electrical charge is not continuous but is carried in discrete amounts equal to the electron charge. Electrical noise represents a fundamental limit on the performance of electronic circuits and systems. With the explosive growth in the personal mobile communications market, the need for noise analysis/simulation techniques for nonlinear electronic circuits and systems has been re-emphasized. Even though most of the signal processing is done in the digital domain, every wireless communication device has an analog front-end which is usually the bottleneck in the design of the whole system. The requirements for low-power operation and higher levels of integration create new challenges in the design of the analog signal processing subsystems of these mobile communication devices. The effect of noise on the performance of these inherently nonlinear analog circuits is becoming more and more significant.Analysis and Simulation of Noise in Nonlinear Electronic Circuits and Systems presents analysis, simulation and characterization techniques and behavioral models for noise in nonlinear electronic circuits and systems, along with practical examples. This book treats the problem within the framework of, and using techniques from, the probabilistic theory of stochastic processes and stochastic differential systems. Analysis and Simulation of Noise in Nonlinear Electronic Circuits and Systems will be of interest to RF/analog designers as well as engineers interested in stochastic modeling and simulation.

Memory Issues in Embedded Systems-On-Chip: Optimizations and Explorations is designed for different groups in the embedded systems-on-chip arena. First, it is designed for researchers and graduate students who wish to understand the research issues involved in memory system optimization and exploration for embedded systems-on-chip. Second, it is intended for designers of embedded systems who are migrating from a traditional micro-controllers centered, board-based design methodology to newer design methodologies using IP blocks for processor-core-based embedded systems-on-chip. Also, since Memory Issues in Embedded Systems-on-Chip: Optimization and Explorations illustrates a methodology for optimizing and exploring the memory configuration of embedded systems-on-chip, it is intended for managers and system designers who may be interested in the emerging capabilities of embedded systems-on-chip design methodologies for memory-intensive applications.

Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplishment, have you ever had someone ask you, "Are you good or are you just lucky?"? Many design projects depend on blind luck in hopes that the chip will work. Other's, just adamantly rely on their own abilities to bring the chip to success. ill either case, how can we tell the difference between being good or lucky? There must be a better way not to fail. Failure. No one likes to fail. ill his book, "The Logic of Failure", Dietrich Domer argues that failure does not just happen. A series of wayward steps leads to disaster. Often these wayward steps are not really logical, decisive steps, but more like default omissions. Anti-planning if you will, an ad-hoc approach to doing something. To not plan then, is to fail.

The development of computational models of design founded on the artificial intelligenceparadigm has provided an impetus for muchofcurrentdesign research. As artificial intelligence has matured and developed new approaches so the impact ofthese new approaches on design research has been felt. This can be seen in the wayconcepts from cognitive science has found theirway into artificial intelligence and hence into design research. And, also in the way in which agent-based systems arebeingincorporated into design systems. In design research there is an increasing blurring between notions drawn from artificial intelligence and those drawn from cognitive science. Whereas a number of years ago the focus was largely on applying artificial intelligence to designing as an activity, thus treating designing as a form ofproblem solving, today we are seeing a much wider variety ofconceptions of the role of artificial intelligence in helping to model and comprehend designing as a process. Thus, we see papers in this volume which have as their focus the development or implementationofframeworks for artificial intelligence in design - attempting to determine a unique locus for these ideas. We see papers which attempt to find foundations for the development of tools based on the artificial intelligence paradigm; often the foundations come from cognitive studiesofhuman designers.

The Verilog language is a hardware description language which provides a means of specifying a digital system at a wide range of levels of abstraction. The language supports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of a description. Verilog was originally designed in the winter of 1983/84 as a proprietary verification/simulation product. Since then, several other proprietary analysis tools have been developed around the language, including a fault simulator and a timing analyzer; the language being instrumental in providing consistency across these tools. Now, the language is openly available for any tool to read and write. This book introduces the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Where possible, we have stayed away from simulator-specific details and concentrated on design specification, but have included enough information to be able to have working executable models. The book takes a tutorial approach to presenting the language.

Design is an important research topic in engineering and architecture, since design is not only a means of change but also one of the keystones of economic competitiveness and the fundamental precursor to manufacturing. However, our understanding of design as a process and our ability to model it are still very limited. The development of computational models founded on the artificial intelligence paradigm has provided an impetus for much of current design research -- both computational and cognitive. Notwithstanding their immaturity noticeable advances have been made both in extending our understanding of design and in developing tools based on that understanding. The papers in this volume are from the Third International Conference on Artificial Intelligence in Design held in August 1994 in Lausanne, Switzerland. They represent the cutting edge of research and development in this field. They are of particular interest to researchers, developers and users of computer systems in design. This volume demonstrates both the breadth and depth of artificial intelligence in design and points the way forward for our understanding of design as a process and for the development of computer-based tools to aid designers.

by Phil Moorby The Verilog Hardware Description Language has had an amazing impact on the mod em electronics industry, considering that the essential composition of the language was developed in a surprisingly short period of time, early in 1984. Since its introduc tion, Verilog has changed very little. Over time, users have requested many improve ments to meet new methodology needs. But, it is a complex and time consuming process to add features to a language without ambiguity, and maintaining consistency. A group of Verilog enthusiasts, the IEEE 1364 Verilog committee, have broken the Verilog feature doldrums. These individuals should be applauded. They invested the time and energy, often their personal time, to understand and resolve an extensive wish-list of language enhancements. They took on the task of choosing a feature set that would stand up to the scrutiny of the standardization process. I would like to per sonally thank this group. They have shown that it is possible to evolve Verilog, rather than having to completely start over with some revolutionary new language. The Verilog 1364-2001 standard provides many of the advanced building blocks that users have requested. The enhancements include key components for verification, abstract design, and other new methodology capabilities. As designers tackle advanced issues such as automated verification, system partitioning, etc., the Verilog standard will rise to meet the continuing challenge of electronics design.

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Embedded systems are characterized by the presence of processors running application-specific software. Recent years have seen a large growth of such systems, and this trend is projected to continue with the growth of systems on a chip. Many of these systems have strict performance and cost requirements. To design these systems, sophisticated timing analysis tools are needed to accurately determine the extreme case (best case and worst case) performance of the software components. Existing techniques for this analysis have one or more of the following limitations: * they cannot model complicated programs * they cannot model advanced micro-architectural features of the processor, such as cache memories and pipelines * they cannot be easily retargeted for new hardware platforms. In Performance Analysis of Real-Time Embedded Software, a new timing analysis technique is presented to overcome the above limitations. The technique determines the bounds on the extreme case (best case and worst case) execution time of a program when running on a given hardware system. It partitions the problem into two sub-problems: program path analysis and microarchitecture modeling.Performance Analysis of Real-Time Embedded Software will be of interest to Design Automation professionals as well as designers of circuits and systems.