Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.

Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems. Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. The state of the art in timing analysis and optimization techniques is described for circuits using edge-triggered or level-sensitive memory elements. Specific emphasis is placed on two methods that are true sequential timing optimizations techniques: retiming and clock skew optimization.Timing Analysis and Optimization of Sequential Circuits covers the following topics: * Algorithms for sequential timing analysis * Fast algorithms for clock skew optimization and their applications * Efficient techniques for retiming large sequential circuits * Coupling sequential and combinational optimizations. Timing Analysis and Optimization of Sequential Circuits is written for graduate students, researchers and professionals in the area of CAD for VLSI and VLSI circuit design.

Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: `With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.' Kurt Keutzer, University of California, Berkeley

This book contains the proceedings of the workshop Uncertainty in Geomet ric Computations that was held in Sheffield, England, July 5-6, 2001. A total of 59 delegates from 5 countries in Europe, North America and Asia attended the workshop. The workshop provided a forum for the discussion of com putational methods for quantifying, representing and assessing the effects of uncertainty in geometric computations. It was organised around lectures by invited speakers, and presentations in poster form from participants. Computer simulations and modelling are used frequently in science and engi neering, in applications ranging from the understanding of natural and artificial phenomena, to the design, test and manufacturing stages of production. This widespread use necessarily implies that detailed knowledge of the limitations of computer simulations is required. In particular, the usefulness of a computer simulation is directly dependent on the user's knowledge of the uncertainty in the simulation. Although an understanding of the phenomena being modelled is an important requirement of a good computer simulation, the model will be plagued by deficiencies if the errors and uncertainties in it are not consid ered when the results are analysed. The applications of computer modelling are large and diverse, but the workshop focussed on the management of un certainty in three areas : Geometric modelling, computer vision, and computer graphics.

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9 QUADRATIC 0-1 PROGRAMMING 8S 9. 1 Energy Minimization 86 9. 2 Notation and Tenninology . . . . . . . . . . . . . . . . . 87 9. 3 Minimization Technique . . . . . . . . . . . . . . . . . . 88 9. 4 An Example . . . . . . . . . . . . . . . . . . . . . . . . 92 9. 5 Accelerated Energy Minimization. . . . . . . . . . . . . 94 9. 5. 1 Transitive Oosure . . . . . . . . . . . . . . . . . 94 9. 5. 2 Additional Pairwise Relationships 96 9. 5. 3 Path Sensitization . . . . . . . . . . . . . . . . . 97 9. 6 Experimental Results 98 9. 7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 100 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10 TRANSITIVE CLOSURE AND TESTING 103 10. 1 Background . . . . . . . . . . . . . . . . . . . . . . . . 104 10. 2 Transitive Oosure Definition 105 10. 3 Implication Graphs 106 10. 4 A Test Generation Algorithm 107 10. 5 Identifying Necessary Assignments 112 10. 5. 1 Implicit Implication and Justification 113 10. 5. 2 Transitive Oosure Does More Than Implication and Justification 115 10. 5. 3 Implicit Sensitization of Dominators 116 10. 5. 4 Redundancy Identification 117 10. 6 Summary 119 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 11 POLYNOMIAL-TIME TESTABILITY 123 11. 1 Background 124 11. 1. 1 Fujiwara's Result 125 11. 1. 2 Contribution of the Present Work . . . . . . . . . 126 11. 2 Notation and Tenninology 127 11. 3 A Polynomial TlDle Algorithm 128 11. 3. 1 Primary Output Fault 129 11. 3. 2 Arbitrary Single Fault 135 11. 3. 3 Multiple Faults. . . . . . . . . . . . . . . . . . . 137 11. 4 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . 139 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 ix 12 SPECIAL CASES OF HARD PROBLEMS 141 12. 1 Problem Statement 142 12. 2 Logic Simulation 143 12. 3 Logic Circuit Modeling . 146 12. 3. 1 Modelfor a Boolean Gate . . . . . . . . . . . . . 147 12. 3. 2 Circuit Modeling 148 12.

Integrated circuit technology is widely used for the full integration of electronic systems. In general, these systems are realized using digital techniques implemented in CMOS technology. The low power dissipation, high packing density, high noise immunity, ease of design and the relative ease of scaling are the driving forces of CMOS technology for digital applications. Parts of these systems cannot be implemented in the digital domain and will remain analog. In order to achieve complete system integration these analog functions are preferably integrated in the same CMOS technology. An important class of analog circuits that need to be integrated in CMOS are analog filters. This book deals with very high frequency (VHF) filters, which are filters with cut-off frequencies ranging from the low megahertz range to several hundreds of megahertz. Until recently the maximal cut-off frequencies of CMOS filters were limited to the low megahertz range. By applying the techniques presented in this book the limit could be pushed into the true VHF domain, and integrated VHF filters become feasible. Application of these VHF filters can be found in the field of communication, instrumentation and control systems. For example, pre and post filtering for high-speed AD and DA converters, signal reconstruction, signal decoding, etc. The general design philosophy used in this book is to allow only the absolute minimum of signal carrying nodes throughout the whole filter. This strategy starts at the filter synthesis level and is extended to the level of electronic circuitry. The result is a filter realization in which all capacitators (including parasitics) have a desired function. The advantage of this technique is that high frequency parasitic effects (parasitic poles/zeros) are minimally present. The book is a reference for engineers in research or development, and is suitable for use as a text for advanced courses on the subject. >

The purpose of this book is to introduce VHSIC Hardware Description Lan guage (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that per mitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the im plementationtechnolo y. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result synthe sis tools accept only subsets of VHDL. This book tries to cover the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. This book is suitable for working professionals as well as for graduate or under graduate study. Readers can view this book as a way to get acquainted with VHDL and how it can be used in modeling of digital designs."

Research on high-level synthesis started over twenty years ago, but lower-level tools were not available to seriously support the insertion of high-level synthesis into the mainstream design methodology. Since then, substantial progress has been made in formulating and understanding the basic concepts in high-level synthesis. Although many open problems remain, high-level synthesis has matured. High-Level Synthesis: Introduction to Chip and System Design presents a summary of the basic concepts and results and defines the remaining open problems. This is the first textbook on high-level synthesis and includes the basic concepts, the main algorithms used in high-level synthesis and a discussion of the requirements and essential issues for high-level synthesis systems and environments. A reference text like this will allow the high-level synthesis community to grow and prosper in the future.

The automation of layout synthesis design under stringent timing specifications is essential for state-of-the-art VLSI circuits and systems design. Especially, the timing-driven layout synthesis with optimal placement and routing of transistors with proper sizing is most critical in view of the chip area, interconnection parasitics, circuit delay and power dissipation. This book presents a systematic and unified view of the layout synthesis problem with a strong focus on CMOS technology. The criticality of RC parasitics in the interconnects and the optimal sizing of both p-channel and n-channel translators are illustrated for motivation. Following the motivation, the problems of modeling circuit delays and translator sizing are formulated and solved with mathematical rigor. Various delay models for CMOS circuits are discussed to account for realistic interconnection parasitics, the effect of transistor sizes, and also the input slew rates. Also many of the efficient transistor sizing algorithms are critically reviewed and the most recent transistor sizing algorithm based on convex programming techniques is introduced.For design automation of the rigorous CMOS layout synthesis, an integrated system that employs a suite of functional modules is introduced for step-by-step illustration of the design optimization process that produces highly compact CMOS layouts that meet user-specified timing and logical netlist requirements. Through most rigorous discussion of the essential design automation process steps and important models and algorithms this book presents a unified systems approach that can be practiced for high-performance CMOS VLSI designs. This book serves as an excellent reference, and can be used as text in advanced courses covering VLSI design, especially for design automation of physical design.

Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. This in our view is due to the inability of current architectural synthesizers to provide area-delay competitive (or "optimal") architectures, that will support interfaces to analog, asynchronous, and other complex processes. They also fail to incorporate testability. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved. Traditionally architectural synthesis is viewed as NP hard and there fore most research has involved heuristics. OASIC demonstrates by using an IP approach (using polyhedral analysis), that most input algo rithms can be synthesized very fast into globally optimal architectures. Since a mathematical model is used, complex interface constraints can easily be incorporated and solved. Research in test incorporation has in general been separate from syn thesis research. This is due to the fact that traditional test research has been at the gate or lower level of design representation. Nevertheless as technologies scale down, and complexity of design scales up, the push for reducing testing times is increased. On way to deal with this is to incorporate test strategies early in the design process. The second half of this text examines an approach for integrating architectural synthesis with test incorporation. Research showed that test must be considered during synthesis to provide good architectural solutions which minimize Xlll area delay cost functions."

Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits. Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise. But the world is not solely digital. Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market. Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel non-linear infinite programming optimization formulation of the circuit synthesis problem via a sequence of smaller optimization problems. Practical Synthesis of High-Performance Analog Circuits will be of interest to analog circuit designers, CAD EDA industry professionals, academics and students.

Research and development of logic synthesis and verification have matured considerably over the past two decades. Many commercial products are available, and they have been critical in harnessing advances in fabrication technology to produce today's plethora of electronic components. While this maturity is assuring, the advances in fabrication continue to seemingly present unwieldy challenges. Logic Synthesis and Verification provides a state-of-the-art view of logic synthesis and verification. It consists of fifteen chapters, each focusing on a distinct aspect. Each chapter presents key developments, outlines future challenges, and lists essential references. Two unique features of this book are technical strength and comprehensiveness. The book chapters are written by twenty-eight recognized leaders in the field and reviewed by equally qualified experts. The topics collectively span the field. Logic Synthesis and Verification fills a current gap in the existing CAD literature. Each chapter contains essential information to study a topic at a great depth, and to understand further developments in the field. The book is intended for seniors, graduate students, researchers, and developers of related Computer-Aided Design (CAD) tools. From the foreword: "The commercial success of logic synthesis and verification is due in large part to the ideas of many of the authors of this book. Their innovative work contributed to design automation tools that permanently changed the course of electronic design." by Aart J. de Geus, Chairman and CEO, Synopsys, Inc.

The economic and social developments in the world continually pose new questions to both the social and physical sciences, to the state and to the economy. Currently, the social, natural, and technological fields are particularly impacted by these developments. The facilitation of scientific insights and the utilization of the assembled knowledge of millions of people in their daily work has evolved key questions about the very existence and continuation of society. In a time where almost anything is technically possible, the means of advancing/facilitating (didactics) technological capabilities are being pursued with even more fervor than the actual hunt for new technological capabilities - at least by the most far-seeing nations. In comparison to natural resources, it is a nation's human resources and their combined capability that is infinite. The development of these capabilities was the impetus for this workshop. To this challenge and process, new, hitherto unknown tasks and needs have emerged to energize the dynamic even further. Currently characterizing this search are key words and concepts that include interdisciplinarity, cognitive science, complexity, personal competence, synergistic competence, human resource development, technological literacy, school-industry links (partnerships), private practice partnerships, cognitive apprenticeship, reengineering education, concurrent education, hypermedia, meta-cognition, etc.

Ad ap tive Contro l provid es tec hniques for aut omatic adjustment in real t ime of cont roller parameter s in order to achieve or to maintain a desired level for the performance of cont rol systems when the dyn amic param et ers of t he process are unknown and/or var y in time. These techniques have as a main feature t he abilit y to ext ract significant information from real dat a in ord er to tune the cont roller and they feature a me chanism for adjust ing parameter s (of a plant model or of a cont roller). While the history of Adaptive Control is lon g, significant progr ess in under - standing and applying Adaptive Con trol began in the early sevent ies. The growing availability of digital com puters have also contributed to the devel- opment of the field . The earlier applicat ions in the sevent ies and beginning of the eight ies, provided important feedback for the development of the field . Theoretical developments allowed a number of basic problems to be solved . The aim of this book is to provide a coherent and comprehensive treatment of the field . The presentation takes the read er from the basic problem formu- lation to the analytical solutions who se prac tical significance is illustrated by applications.

Concurrent simulation is over twenty years old. During that pe riod it has been widely adopted for the simulation of faults in digital circuits, for which it provides a combination of extreme efficiency and generality . Yet, it is remarkable that no book published so far presents a correct and sufficiently detailed treatment of concurrent simulation. A first reason to welcome into print the effort of the authors is, therefore, that it provides a much needed account of an important topic in design automation. This book is, however, unique for sev eral other reasons. It is safe to state that no individual has contrib uted more than Ernst Ulrich to the development of digital logic simulation. For concurrent simulation, one may say that Ernst has contributed more than the rest of the world. We would find such a claim difficult to dispute. The unique experience of the authors con fers a special character to this book: It is authoritative, inspired, and focused on what is conceptually important. Another unique aspect of this book, perhaps the one that will be the most surprising for many readers, is that it is strongly projected towards the future. Concurrent simulation is presented as a general experimentation methodology and new intriguing applications are analyzed. The discussion of multi-domain concurrent simulation-- recent work of Karen Panetta Lentz and Ernst Ulrich---is fascinat ing."

Co-Synthesis of Hardware and Software for Digital Embedded Systems, with a Foreword written by Giovanni De Micheli, presents techniques that are useful in building complex embedded systems. These techniques provide a competitive advantage over purely hardware or software implementations of time-constrained embedded systems. Recent advances in chip-level synthesis have made it possible to synthesize application-specific circuits under strict timing constraints. This work advances the state of the art by formulating the problem of system synthesis using both application-specific as well as reprogrammable components, such as off-the-shelf processors. Timing constraints are used to determine what part of the system functionality must be delegated to dedicated application-specific hardware while the rest is delegated to software that runs on the processor. This co-synthesis of hardware and software from behavioral specifications makes it possible to realize real-time embedded systems using off-the-shelf parts and a relatively small amount of application-specific circuitry that can be mapped to semi-custom VLSI such as gate arrays. The ability to perform detailed analysis of timing performance provides the opportunity of improving the system definition by creating better phototypes. Co-Synthesis of Hardware and Software for Digital Embedded Systems is of interest to CAD researchers and developers who want to branch off into the expanding field of hardware/software co-design, as well as to digital system designers who are interested in the present power and limitations of CAD techniques and their likely evolution.

Digital BiCMOS Integrated Circuit Design is the first book devoted entirely to the analysis and design of digital BiCMOS integrated circuits. BiCMOS Integrated Circuit Design also reviews CMOS and CML integrated circuit design. The application of BiCMOS in the design of digital subsystems, e.g. adders, multipliers, RAMs and PLAs is addressed. The book also introduces the reader to IC process technology: CMOS, bipolar and BiCMOS. The modeling of both the bipolar and MOS devices are covered. Many process/device/circuit design issues are discussed. Digital BiCMOS Integrated Circuit Design can be used by engineers, researchers, graduate and senior undergraduate students working in the area of digital integrated circuits, digital circuits and system design, BiCMOS process and device modeling.

A reactive system is one that is in continual interaction with its environment and executes at a pace determined by that environment. Examples of reactive systems are network protocols, air-traffic control systems, industrial-process control systems etc. Reactive systems are ubiquitous and represent an important class of systems. Due to their complex nature, such systems are extremely difficult to specify and implement. Many reactive systems are employed in highly-critical applications, making it crucial that one considers issues such as reliability and safety while designing such systems. The design of reactive systems is considered to be problematic, and p.oses one of the greatest challenges in the field of system design and development. In this paper, we discuss specification-modeling methodologies for reactive systems. Specification modeling is an important stage in reactive system design where the designer specifies the desired properties of the reactive system in the form of a specification model. This specification model acts as the guidance and source for the implementation. To develop the specification model of complex systems in an organized manner, designers resort to specification modeling methodologies. In the context of reactive systems, we can call such methodologies reactive-system specification modeling methodologies.

Advanced Low-Power Digital Circuit Techniques presents several novel high performance digital circuit designs that emphasize low-power and low-voltage operation. These circuits represent a wide range of circuits that are used in state-of-the-art VLSI systems and hence serve as good examples for low-power design. Each chapter contains a brief introduction that serves as a quick background and gives the motivation behind the design. Each chapter also ends with a summary that briefly explains the contributions contained therein. This makes the book very readable. The reader can skim through the chapters very quickly to get a feel for the design problems presented in the book and the solutions proposed by the authors. Examples of circuits used in systems where low-power is important from reliability and portability points of view (such as general-purpose and DSP processors) are presented in Chapters 2, 3 and 4. Chapters 5 and 7 give examples of circuits used in systems where reliability and more system integration are the main driving forces behind lowering the power consumption. Chapter 6 gives an example of a general purpose high-performance low-power circuit design. Advanced Low-Power Digital Circuit Techniques is a real designer's book. It investigates alternative circuit styles, as well as architectural alternatives, and gives quantitative results for comparison in realistic technologies. Several of the circuits presented have been fabricated so that simulations can be checked. The circuits covered are the most important building blocks for many designs, so the text will be of direct use to designers. MOS designs are covered, as well as BiCMOS, and there are several novel circuits.

This book deals with Web applications in product design and manufacture, thus filling an information gap in digital manufacturing in the Internet era. It helps both developers and users to appreciate the potentials, as well as difficulties, in developing and adopting Web applications. The objective is to equip potential users and practitioners of Web applications with a better appreciation of the technology. In addition, Web application developers and new researchers in this field will gain a clearer understanding of the selection of system architecture and design, development and implementation techniques, and deployment strategies. The book is divided into two main parts. The first part gives an overview of Web and Internet and the second explains eight typical Web applications.

"System level testing is becoming increasingly important. It is driven by the incessant march of complexity ... which is forcing us to renew our thinking on the processes and procedures that we apply to test and diagnosis of systems. In fact, the complexity defines the system itself which, for our purposes, is ?any aggregation of related elements that together form an entity of sufficient complexity for which it is impractical to treat all of the elements at the lowest level of detail . System approaches embody the partitioning of problems into smaller inter-related subsystems that will be solved together. Thus, words like hierarchical, dependence, inference, model, and partitioning are frequent throughout this text. Each of the authors deals with the complexity issue in a similar fashion, but the real value in a collected work such as this is in the subtle differences that may lead to synthesized approaches that allow even more progress. The works included in this volume are an outgrowth of the 2nd International Workshop on System Test and Diagnosis held in Alexandria, Virginia in April 1998. The first such workshop was held in Freiburg, Germany, six years earlier. In the current workshop nearly 50 experts from around the world struggled over issues concerning the subject... In this volume, a select group of workshop participants was invited to provide a chapter that expanded their workshop presentations and incorporated their workshop interactions... While we have attempted to present the work as one volume and requested some revision to the work, the content of the individual chapters was not edited significantly. Consequently, you will see different approaches to solving the same problems and occasional disagreement between authors as to definitions or the importance of factors. ... The works collected in this volume represent the state-of-the-art in system test and diagnosis, and the authors are at the leading edge of that science...". From the Preface

Geometric constraint programming increases flexibility in CAD design specifications and leads to new conceptual design paradigms.
This volume features a collection of work by leading researchers developing the various aspects of constraint-based product modeling.
In an introductory chapter the role of constraints in CAD systems of the future and their implications for the STEP data exchange format are discussed. The main part of the book deals with the application of constraints to conceptual and collaborative design, as well as state-of-the-art mathematical and algorithmic methods for constraint solving.

Parallel CFD 2008, the twentieth in the high-level international series of meetings featuring different aspect of parallel computing in computational?uid dynamics and other modern scienti?c domains was held May 19?22, 2008 in Lyon, France. The themes of the 2008 meeting included the traditional emphases of this c- ference, and experiences with contemporary architectures. Around 70 presentations were included into the conference program in the following sessions: Parallel Algorithms and solvers Parallel performances with contemporary architectures Structured and unstructured grid methods, boundary methods software framework and components architecture CFD applications(Bio ?uid, environmentalproblem)Lattice Boltzmannmethodand SPH Optimisation in Aerodynamics This book presents an up-to-date overviewof the state of the art in Parallel C- putational Fluid Dynamics from Asia, Europe, and North America. This reviewed proceedingsincluded about sixty percent of the oral lectures presented at the conf- ence. The editors. VI Preface Parallel CFD 2008 was organized by the Institut Camille Jordan of the Univ- sity of Lyon 1 in collaboration with the Center for the Development of the Parallel Scienti?c Computing. The Scienti?c Committee and Local Organizers of Parallel CFD 2008 are - lighted to acknowledge the generous sponsorship of the following organizations, through ?nancial or in-kind assistance. Assistance of our sponsors allowed to - ganize scienti?c as well as social program of the conference.

The assembly sector is one of the least automated in the manufacturing industry. Automation is essential if industrial companies are to be competitive in the future. In assembly, an integrated and flexible approach is needed because 75% of the applications are produced in small and medium batches. The methodologies developed in this book deal with the integration of the assembly process from the initial design of the product to its production. In such an integrated system, assembly planning is one of the most important features. A well-chosen assembly plan will reduce both the number of tool changes and the fixtures within the assembly cell. It will prevent the handling of unstable subassemblies, simplify the design of the robot grippers and reduce production costs. An automatic generator of assembly sequences can be an efficient aid to the designer. Whenever he or she modifies features of the product, the influence of these modifications can immediately be checked on the sequences. For small batch production, the automatic generation of assembly sequences is faster, more reliable and more cost-effective than manual generation. By using this latter method interesting sequences could be missed because of the combinatorial explosion of solutions. The main subjects treated in this book are as follows. 1. Presentation and classification of existing systems of automatic generation of assembly sequences. Automatic assembly planning is, indeed, a very recent research area and, in my experience, no systematic study has been carried out up to now.

This book is a collection of several tutorials from the EUROGRAPHICS '90 conference in Montreux. The conference was held under the motto "IMAGES: Synthesis, Analysis and Interaction", and the tutorials, partly presented in this volume, reflect the conference theme. As such, this volume provides a unique collection of advanced texts on 'traditional' com puter graphics as well as of tutorials on image processing and image reconstruction. As with all the volumes of the series "Advances in Computer Graphics", the contributors are leading experts in their respective fields. The chapter Design and Display of Solid Models provides an extended introduction to interactive graphics techniques for design, fast display, and high-quality rendering of solid models. The text focuses on techniques for Constructive Solid Geometry (CSG). The follow ing topics are treated in depth: interactive design techniques (specification of curves, surfaces and solids; graphical user interfaces; procedural languages and direct manipulation) and display techniques (depth-buffer, scan-line and ray-tracing techniques; CSG classification techniques; efficiency-improving methods; software and hardware implementations).