Motivation for this Book Ontologies have received increasing attention over the last two decades. Their roots can be traced back to the ancient philosophers, who were interested in a c- ceptualization of the world. In the more recent past, ontologies and ontological engineering have evolved in computer science, building on various roots such as logics, knowledge representation, information modeling and management, and (knowledge-based) information systems. Most recently, largely driven by the next generation internet, the so-called Semantic Web, ontological software engineering has developed into a scientific field of its own, which puts particular emphasis on the theoretical foundations of representation and reasoning, and on the methods and tools required for building ontology-based software applications in diverse domains. Though this field is largely dominated by computer science, close re- tionships have been established with its diverse areas of application, where - searchers are interested in exploiting the results of ontological software engine- ing, particularly to build large knowledge-intensive applications at high productivity and low maintenance effort. Consequently, a large number of scientific papers and monographs have been p- lished in the very recent past dealing with the theory and practice of ontological software engineering. So far, the majority of those books are dedicated to the th- retical foundations of ontologies, including philosophical treatises and their re- tionships to established methods in information systems and ontological software engineering.

This book presents a collection of chapters describing the state of the art on computational modelling and fabrication in tissue engineering. Tissue Engineering is a multidisciplinary field involving scientists from different fields. The development of mathematical methods is quite relevant to understand cell biology and human tissues as well to model, design and fabricate optimized and smart scaffolds. The chapter authors are the distinguished keynote speakers at the first Eccomas thematic conference on Tissue Engineering where the emphasis was on mathematical and computational modeling for scaffold design and fabrication. This particular area of tissue engineering, whose goal is to obtain substitutes for hard tissues such as bone and cartilage, is growing in importance.

Current multimedia and telecom applications require complex, heterogeneous multiprocessor system on chip (MPSoC) architectures with specific communication infrastructure in order to achieve the required performance. Heterogeneous MPSoC includes different types of processing units (DSP, microcontroller, ASIP) and different communication schemes (fast links, non standard memory organization and access).

Programming an MPSoC requires the generation of efficient software running on MPSoC from a high level environment, by using the characteristics of the architecture. This task is known to be tedious and error prone, because it requires a combination of high level programming environments with low level software design.

This book gives an overview of concepts related to embedded software design for MPSoC. It details a full software design approach, allowing systematic, high-level mapping of software applications on heterogeneous MPSoC. This approach is based on gradual refinement of hardware/software interfaces and simulation models allowing to validate the software at different abstraction levels.

This book combines Simulink for high level programming and SystemC for the low level software development. This approach is illustrated with multiple examples of application software and MPSoC architectures that can be used for deep understanding of software design for MPSoC.

Modern electronics is driven by the explosive growth of digital communications and multi-media technology. A basic challenge is to design first-time-right complex digital systems, that meet stringent constraints on performance and power dissipation. In order to combine this growing system complexity with an increasingly short time-to-market, new system design technologies are emerging based on the paradigm of embedded programmable processors. This concept introduces modularity, flexibility and re-use in the electronic system design process. However, its success will critically depend on the availability of efficient and reliable CAD tools to design, programme and verify the functionality of embedded processors. Recently, new research efforts emerged on the edge between software compilation and hardware synthesis, to develop high-quality code generation tools for embedded processors. Code Generation for Embedded Systems provides a survey of these new developments. Although not limited to these targets, the main emphasis is on code generation for modern DSP processors. Important themes covered by the book include: the scope of general purpose versus application-specific processors, machine code quality for embedded applications, retargetability of the code generation process, machine description formalisms, and code generation methodologies. Code Generation for Embedded Systems is the essential introduction to this fast developing field of research for students, researchers, and practitioners alike.

VHDL Answers to Frequently Asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp.lang.vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error-free, and simulation-efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complex simulatable examples. This book is intended for those who are seeking an enhanced proficiency in VHDL. This book differs from other VHDL books in many respects.This book: * emphasizes real VHDL, rather than philosophical or introductory types of information * emphasizes application of VHDL for synthesis * uses complete examples to demonstrate problems and solutions * provides a disk that includes all the book examples and other useful reference VHDL material * uses easy to remember symbology notation to emphasize language rules, good and poor methodology and coding styles * identifies obsolete VHDL constructs that must be avoided * identifies synthesizable/non-synthesizable structures * uses a question and answer format to clarify and emphasize the concerns of VHDL users.

Boundary-Scan, formally known as IEEE/ANSI Standard 1149.1-1990, is a collection of design rules applied principally at the integrated circuit (IC) level that allow software to alleviate the growing cost of designing and producing digital systems. The primary benefit of the standard is its ability to transform extremely printed circuit board testing problems that could only be attacked with ad-hoc testing methods into well-structured problems that software can easily and swiftly deal with. The Boundary-Scan Handbook is for professionals in the electronics industry who are concerned with the practical problems of competing successfully in the face of rapid-fire technological change. Since many of these changes affect our ability to do testing and hence cost-effective production, the advent of the 1149.1 standard is rightly looked upon as a major breakthrough. However, there is a great deal of misunderstanding about what to expect of 1149.1 and how to use it. Because of this, The Boundary-Scan Handbook is not a rehash of the 1149.1 standard, nor does it intend to be a tutorial on the basics of its workings. The standard itself should always be consulted for this, being careful to follow supplements issued by the IEEE that clarify and correct it. Rather, The Boundary-Scan Handbook motivates proper expectations and explains how to use the standard successfully.

This book introduces a design methodology that can help to bridge the productivity gap. Two different types of designs, depending on the design challenge, have been identified. To validate the presented methodologies, the authors have selected and designed accordingly three different industrial-strength applications.

Simulation Methods for Reliability and Availability of Complex Systems discusses the use of computer simulation-based techniques and algorithms to determine reliability and availability (R and A) levels in complex systems. The book: shares theoretical or applied models and decision support systems that make use of simulation to estimate and to improve system R and A levels, forecasts emerging technologies and trends in the use of computer simulation for R and A and proposes hybrid approaches to the development of efficient methodologies designed to solve R and A-related problems in real-life systems. Dealing with practical issues, Simulation Methods for Reliability and Availability of Complex Systems is designed to support managers and system engineers in the improvement of R and A, as well as providing a thorough exploration of the techniques and algorithms available for researchers, and for advanced undergraduate and postgraduate students.

Systematic Design of Sigma-Delta Analog-to-Digital Converters describes the issues related to the sigma-delta analog-to-digital converters (ADCs) design in a systematic manner: from the top level of abstraction represented by the filters defining signal and noise transfer functions (STF, NTF), passing through the architecture level where topology-related performance is calculated and simulated, and finally down to parameters of circuit elements like resistors, capacitors, and amplifier transconductances used in individual integrators. The systematic approach allows the evaluation of different loop filters (order, aggressiveness, discrete-time or continuous-time implementation) with quantizers varying in resolution. Topologies explored range from simple single loops to multiple cascaded loops with complex structures including more feedbacks and feedforwards. For differential circuits, with switched-capacitor integrators for discrete-time (DT) loop filters and active-RC for continuous-time (CT) ones, the passive integrator components are calculated and the power consumption is estimated, based on top-level requirements like harmonic distortion and noise budget.
This unified, systematic approach to choosing the best sigma-delta ADC implementation for a given design target yields an interesting solution for a high-resolution, broadband (DSL-like) ADC operated at low oversampling ratio, which is detailed down to transistor-level schematics.
The target audience of Systematic Design of Sigma-Delta Analog-to-Digital Converters are engineers designing sigma-delta ADCs and/or switched-capacitor and continuous-time filters, both beginners and experienced. It is also intended for students/academics involved in sigma-delta and analog CAD research.

This book presents a powerful new language and methodology for programming complex reactive systems in a scenario-based manner. The language is live sequence charts (LSCs), a multimodal extension of sequence charts and UML's sequence diagrams, used in the past mainly for requirements. The methodology is play-in/play-out, an unusually convenient means for specifying inter-object scenario-based behavior directly from a GUI or an object model diagram, with the surprising ability to execute that behavior, or those requirements, directly. The language and methodology are supported by a fully implemented tool the Play-Engine which is attached to the book in CD form.

Comments from experts in the field:

The design of reactive systems is one of the most challenging problems in computer science. This books starts with a critical insight to explain the difficulty of this problem: there is a fundamental gap between the scenario-based way in which people think about such systems and the state-based way in which these systems are implemented. The book then offers a radical proposal to bridge this gap by means of playing scenarios. Systems can be specified by playing in scenarios and implemented by means of a Play-Engine that plays out scenarios. This idea is carried out and developed, lucidly, formally and playfully, to its fullest. The result is a compelling proposal, accompanied by a prototype software engine, for reactive systems design, which is bound to cause a splash in the software-engineering community.

Moshe Y. Vardi, Rice University, Houston, Texas, USA

Scenarios are a primary exchange tool in explaining system behavior to others, but their limited expressive power never made them able to fully describe systems, thus limiting their use. The language of Live Sequence Charts (LSCs) presented in this beautifully written book achieves this goal, and the attached Play-Engine software makes these LSCs really come alive. This is undoubtedly a key breakthrough that will start long-awaited and exciting new directions in systems specification, synthesis, and analysis.

Gerard Berry, Esterel Technologies and INRIA, Sophia-Antipolis, France

The approach of David Harel and Rami Marelly is a fascinating way of combining prototyping techniques with techniques for identifying behavior and user interfaces.

Manfred Broy, Technical University of Munich, Germany"

Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become one of the most popular implementation media for digital circuits and have grown into a $2 billion per year industry. As process geometries have shrunk into the deep-submicron region, the logic capacity of FPGAs has greatly increased, making FPGAs a viable implementation alternative for larger and larger designs. To make the best use of these new deep-submicron processes, one must re-design one's FPGAs and Computer- Aided Design (CAD) tools. Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes. Three factors combine to determine the performance of an FPGA: the quality of the CAD tools used to map circuits into the FPGA, the quality of the FPGA architecture, and the electrical (i.e. transistor-level) design of the FPGA. Architecture and CAD for Deep-Submicron FPGAs examines all three of these issues in concert. In order to investigate the quality of different FPGA architectures, one needs CAD tools capable of automatically implementing circuits in each FPGA architecture of interest. Once a circuit has been implemented in an FPGA architecture, one next needs accurate area and delay models to evaluate the quality (speed achieved, area required) of the circuit implementation in the FPGA architecture under test. This book therefore has three major foci: the development of a high-quality and highly flexible CAD infrastructure, the creation of accurate area and delay models for FPGAs, and the study of several important FPGA architectural issues. Architecture and CAD for Deep-Submicron FPGAs is an essential reference for researchers, professionals and students interested in FPGAs.

Structural optimization is currently attracting considerable attention. Interest in - search in optimal design has grown in connection with the rapid development of aeronautical and space technologies, shipbuilding, and design of precision mach- ery. A special ?eld in these investigations is devoted to structural optimization with incomplete information (incomplete data). The importance of these investigations is explained as follows. The conventional theory of optimal structural design - sumes precise knowledge of material parameters, including damage characteristics and loadings applied to the structure. In practice such precise knowledge is seldom available. Thus, it is important to be able to predict the sensitivity of a designed structure to random ?uctuations in the environment and to variations in the material properties. To design reliable structures it is necessary to apply the so-called gu- anteed approach, based on a "worst case scenario" or a more optimistic probabilistic approach, if we have additional statistical data. Problems of optimal design with incomplete information also have consid- able theoretical importance. The introduction and investigations into new types of mathematical problems are interesting in themselves. Note that some ga- theoretical optimization problems arise for which there are no systematic techniques of investigation. This monograph is devoted to the exposition of new ways of formulating and solving problems of structural optimization with incomplete information. We recall some research results concerning the optimum shape and structural properties of bodies subjected to external loadings.

Modeling in Analog Design highlights some of the most pressing issues in the use of modeling techniques for design of analogue circuits. Using models for circuit design gives designers the power to express directly the behaviour of parts of a circuit in addition to using other pre-defined components. There are numerous advantages to this new category of analog behavioral language. In the short term, by favouring the top-down design and raising the level of description abstraction, this approach provides greater freedom of implementation and a higher degree of technology independence. In the longer term, analog synthesis and formal optimisation are targeted. Modeling in Analog Design introduces the reader to two main language standards: VHDL-A and MHDL. It goes on to provide in-depth examples of the use of these languages to model analog devices. The final part is devoted to the very important topic of modeling the thermal and electrothermal aspects of devices. This book is essential reading for analog designers using behavioral languages and analog CAD tool development environments who have to provide the tools used by the designers.

Leaf Cell and Hierarchical Compaction Techniques presents novel algorithms developed for the compaction of large layouts. These algorithms have been implemented as part of a system that has been used on many industrial designs. The focus of Leaf Cell and Hierarchical Compaction Techniques is three-fold. First, new ideas for compaction of leaf cells are presented. These cells can range from small transistor-level layouts to very large layouts generated by automatic Place and Route tools. Second, new approaches for hierarchical pitchmatching compaction are described and the concept of a Minimum Design is introduced. The system for hierarchical compaction is built on top of the leaf cell compaction engine and uses the algorithms implemented for leaf cell compaction in a modular fashion. Third, a new representation for designs called Virtual Interface, which allows for efficient topological specification and representation of hierarchical layouts, is outlined. The Virtual Interface representation binds all of the algorithms and their implementations for leaf and hierarchical compaction into an intuitive and easy-to-use system. From the Foreword: `...In this book, the authors provide a comprehensive approach to compaction based on carefully conceived abstractions. They describe the design of algorithms that provide true hierarchical compaction based on linear programming, but cut down the complexity of the computations through introduction of innovative representations that capture the provably minimum amount of required information needed for correct compaction. In most compaction algorithms, the complexity goes up with the number of design objects, but in this approach, complexity is due to the irregularity of the design, and hence is often tractable for most designs which incorporate substantial regularity. Here the reader will find an elegant treatment of the many challenges of compaction, and a clear conceptual focus that provides a unified approach to all aspects of the compaction task...' Jonathan Allen, Massachusetts Institute of Technology

Advanced ASIC Chip Synthesis: Using Synopsys (R) Design Compiler (R) Physical Compiler (R) and PrimeTime (R), Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution. Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.

This book is the fruit of a very long and elaborate process. It was conceived as a comprehensive solution to several deficiencies encountered while trying to teach the essentials of Computer Vision in different contexts: to technicians from industry looking for technological solutions to some of their problems, to students in search of a good subject for a PhD thesis, and to researchers in other fields who believe that Computer Vision techniques may help them to analyse their results. The book was carefully planned with all these people in mind. Thus, it covers the fundamentals of both 2D and 3D Computer Vision and their most widespread industrial applications, such as automated inspection, robot guidance and workpiece acquisition. The level of explanation is that of an expanded introductory text, in the sense that, besides the basic material, some special advanced topics are included in each chapter, together with an extensive bibliography for experts to follow up. Well-known researchers on each of the topics were appointed to write a chapter following several guidelines to ensure a consistent presentation throughout. I would like to thank the authors for their patience, because some of them had to go through several revisions of their chapters in order to avoid repetition and to improve the homogeneity and coherence of the book. I hope they will find that the final result has been worth their efforts.

This book arises from experience the authors have gained from years of work as industry practitioners in the field of Electronic System Level design (ESL). At the heart of all things related to Electronic Design Automation (EDA), the core issue is one of models: what are the models used for, what should the models contain, and how should they be written and distributed. Issues such as interoperability and tool transportability become central factors that may decide which ones are successful and those that cannot get sufficient traction in the industry to survive. Through a set of real examples taken from recent industry experience, this book will distill the state of the art in terms of System-Level Design models and provide practical guidance to readers that can be put into use. This book is an invaluable tool that will aid readers in their own designs, reduce risk in development projects, expand the scope of design projects, and improve developmental processes and project planning.

Although security is prevalent in PCs, wireless communications and other systems today, it is expected to become increasingly important and widespread in many embedded devices. For some time, typical embedded system designers have been dealing with tremendous challenges in performance, power, price and reliability. However now they must additionally deal with definition of security requirements, security design and implementation. Given the limited number of security engineers in the market, large background of cryptography with which these standards are based upon, and difficulty of ensuring the implementation will also be secure from attacks, security design remains a challenge. This book provides the foundations for understanding embedded security design, outlining various aspects of security in devices ranging from typical wireless devices such as PDAs through to contactless smartcards to satellites.

Appropriate for use as a graduate text or a professional reference, Languages for Digital Embedded Systems is the first detailed, broad survey of hardware and software description languages for embedded system design. Instead of promoting the one language that will solve all design problems (which does not and will not ever exist), this book takes the view that different problems demand different languages, and a designer who knows the spectrum of available languages has the advantage over one who is trapped using the wrong language. Languages for Digital Embedded Systems concentrates on successful, widely-used design languages, with a secondary emphasis on those with significant theoretical value. The syntax, semantics, and implementation of each language is discussed, since although hardware synthesis and software compilation technology have steadily improved, coding style still matters, and a thorough understanding of how a language is synthesized or compiled is generally necessary to take full advantage of a language. Practicing designers, graduate students, and advanced undergraduates will all benefit from this book. It assumes familiarity with some hardware or software languages, but takes a practical, descriptive view that avoids formalism.

Philosophy of the Text This text presents an introductory survey of the basic concepts and applied mathematical methods of nonlinear science as well as an introduction to some simple related nonlinear experimental activities. Students in engineering, phys ics, chemistry, mathematics, computing science, and biology should be able to successfully use this book. In an effort to provide the reader with a cutting edge approach to one of the most dynamic, often subtle, complex, and still rapidly evolving, areas of modern research-nonlinear physics-we have made extensive use of the symbolic, numeric, and plotting capabilities of the Maple software sys tem applied to examples from these disciplines. No prior knowledge of Maple or computer programming is assumed, the reader being gently introduced to Maple as an auxiliary tool as the concepts of nonlinear science are developed. The CD-ROM provided with this book gives a wide variety of illustrative non linear examples solved with Maple. In addition, numerous annotated examples are sprinkled throughout the text and also placed on the CD. An accompanying set of experimental activities keyed to the theory developed in Part I of the book is given in Part II. These activities allow the student the option of "hands on" experience in exploring nonlinear phenomena in the REAL world. Although the experiments are easy to perform, they give rise to experimental and theoretical complexities which are not to be underestimated.

by Maq Mannan President and CEO, DSM Technologies Chairman of the IEEE 1364 Verilog Standards Group Past Chairman of Open Verilog International One of the major strengths of the Verilog language is the Programming Language Interface (PLI), which allows users and Verilog application developers to infinitely extend the capabilities of the Verilog language and the Verilog simulator. In fact, the overwhelming success of the Verilog language can be partly attributed to the exi- ence of its PLI. Using the PLI, add-on products, such as graphical waveform displays or pre and post simulation analysis tools, can be easily developed. These products can then be used with any Verilog simulator that supports the Verilog PLI. This ability to create thi- party add-on products for Verilog simulators has created new markets and provided the Verilog user base with multiple sources of software tools. Hardware design engineers can, and should, use the Verilog PLI to customize their Verilog simulation environment. A Company that designs graphics chips, for ex- ple, may wish to see the simulation results of a new design in some custom graphical display. The Verilog PLI makes it possible, and even trivial, to integrate custom so- ware, such as a graphical display program, into a Verilog simulator. The simulation results can then dynamically be displayed in the custom format during simulation. And, if the company uses Verilog simulators from multiple simulator vendors, this integrated graphical display will work with all the simulators.

History of the Book The last three decades have witnessed an explosive development in integrated circuit fabrication technologies. The complexities of cur rent CMOS circuits are reaching beyond the 100 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the successful design and implemen tation of thousands of high performance, large scale integrated circuits. This research monograph originated from a body of doctoral disserta tion research completed by the first author at the University of Rochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution net work in large scale, high performance digital synchronous circuits and particularly, on algorithms for non-zero clock skew scheduling. During the development of this research, it has become clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical de velopments in this area have been slow to reach the designers' desktops."

Dr. Lester A. Gerhardt Professor and Chairman Electrical, Computer, and Systems Engineering Rensselaer Polytechnic Institute Troy, New York 12180 This book is a collection of papers on the subject of Robotics and Artificial Intelligence. Most of the papers contained herein were presented as part of the program of the NATO Advanced Study Institute held in June 1983 at Castel vecchio Pascoli, Italy on the same subject. Attendance at this two week Institute was by invitation only, drawing people internationally representing industry, government and the academic community worldwide. Many of the people in attendance, as well as those presenting papers, are recognized leaders in the field. In addition to the formal paper presentations, there were several informal work shops. These included a workshop on sensing, a workshop on educational methodology in the subject area, as examples. This book is an outgrowth and direct result of that Institute and includes the papers presented as well as a few others which were stimulated by that meeting. A special note is the paper entitled "State-of-the-Art and Predictions for Artificial Intelligence and Robotics" by Dr. R. Nagel which appears in the Introduction and Overview chapter of this book. This paper was originally developed as part of a study for the United States Army performed by the National Research Council of the National Academy of Science and published as part of a report entitled "Applications of Robotics and Artificial Intelligence to Reduce Risk and Improve Effectiveness" by National Academy Press in 1983."

Analog circuit design is often the bottleneck when designing mixed analog-digital systems. A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits presents a new methodology based on a top-down, constraint-driven design paradigm that provides a solution to this problem. This methodology has two principal advantages: (1) it provides a high probability for the first silicon which meets all specifications, and (2) it shortens the design cycle. A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits is part of an ongoing research effort at the University of California at Berkeley in the Electrical Engineering and Computer Sciences Department. Many faculty and students, past and present, are working on this design methodology and its supporting tools. The principal goals are: (1) developing the design methodology, (2) developing and applying new tools, and (3) `proving' the methodology by undertaking `industrial strength' design examples. The work presented here is neither a beginning nor an end in the development of a complete top-down, constraint-driven design methodology, but rather a step in its development. This work is divided into three parts. Chapter 2 presents the design methodology along with foundation material. Chapters 3-8 describe supporting concepts for the methodology, from behavioral simulation and modeling to circuit module generators. Finally, Chapters 9-11 illustrate the methodology in detail by presenting the entire design cycle through three large-scale examples. These include the design of a current source D/A converter, a Sigma-Delta A/D converter, and a video driver system. Chapter 12 presents conclusions and current research topics. A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits will be of interest to analog and mixed-signal designers as well as CAD tool developers.

From a review of the Second Edition 'If you are new to the field and want to know what "all this Verilog stuff is about," you've found the golden goose. The text here is straight forward, complete, and example rich -mega-multi-kudos to the author James Lee. Though not as detailed as the Verilog reference guides from Cadence, it likewise doesn't suffer from the excessive abstractness those make you wade through. This is a quick and easy read, and will serve as a desktop reference for as long as Verilog lives. Best testimonial: I'm buying my fourth and fifth copies tonight (I've loaned out/lost two of my others).' Zach Coombes, AMD