The area of analog integrated circuits is facing some serious challenges due to the ongoing trends towards low supply voltages, low power consumption and high-frequency operation. The situation is becoming even more complicated by the fact that many transfer functions have to be tunable or controllable. A promising approach to facing these challenges is given by the class of dynamic translinear circuits, which are, as a consequence, receiving increasing interest. Several different names are used in literature: log-domain, exponential state-space, current-mode companding, instantaneous companding, tanh-domain, sinh-domain, polynomial state-space, square-root domain and translinear filters. In fact, all these groups are (overlapping) subclasses of the overall class of dynamic translinear circuits. Research Perspectives on Dynamic Translinear and Log-Domain Circuits is a compilation of research findings in this growing field. It comprises ten contributions, coming from recognized dynamic-translinear' researchers in Europe and North America. Research Perspectives on Dynamic Translinear and Log-Domain Circuits is an edited volume of original research.

There are three outstanding points of this book. First: for the first time, a collective point of view on the role of artificial intelligence paradigm in logic design is introduced. Second, the book reveals new horizons of logic design tools on the technologies of the near future. Finally, the contributors of the book are twenty recognizable leaders in the field from the seven research centres. The chapters of the book have been carefully reviewed by equally qualified experts. All contributors are experienced in practical electronic design and in teaching engineering courses. Thus, the book's style is accessible to graduate students, practical engineers and researchers.

Design reuse is not just a topic of research but a real industrial necessity in the microelectronic domain and thus driving the competitiveness of relevant areas like for example telecommunication or automotive. Most companies have already dedicated a department or a central unit that transfer design reuse into reality. All main EDA conferences include a track to the topic, and even specific conferences have been established in this area, both in the USA and in Europe. Virtual Components Design and Reuse presents a selection of articles giving a mature and consolidated perspective to design reuse from different points of view. The authors stem from all relevant areas: research and academia, IP providers, EDA vendors and industry. Some classical topics in design reuse, like specification and generation of components, IP retrieval and cataloguing or interface customisation, are revisited and discussed in depth. Moreover, new hot topics are presented, among them IP quality, platform-based reuse, software IP, IP security, business models for design reuse, and major initiatives like the MEDEA EDA Roadmap.

Memory Design Techniques for Low Energy Embedded Systems centers one of the most outstanding problems in chip design for embedded application. It guides the reader through different memory organizations and technologies and it reviews the most successful strategies for optimizing them in the power and performance plane.

Contributions on UML address the application of UML in the specification of embedded HW/SW systems. C-Based System Design embraces the modeling of operating systems, modeling with different models of computation, generation of test patterns, and experiences from case studies with SystemC. Analog and Mixed-Signal Systems covers rules for solving general modeling problems in VHDL-AMS, modeling of multi-nature systems, synthesis, and modeling of Mixed-Signal Systems with SystemC. Languages for formal methods are addressed by contributions on formal specification and refinement of hybrid, embedded and real-time stems.
Together with articles on new languages such as SystemVerilog and Software Engineering in Automotive Systems the contributions selected for this book embrace all aspects of languages and models for specification, design, modeling and verification of systems. Therefore, the book gives an excellent overview of the actual state-of-the-art and the latest research results.

Hardware Design and Petri Nets presents a summary of the state of the art in the applications of Petri nets to designing digital systems and circuits. The area of hardware design has traditionally been a fertile field for research in concurrency and Petri nets. Many new ideas about modelling and analysis of concurrent systems, and Petri nets in particular, originated in theory of asynchronous digital circuits. Similarly, the theory and practice of digital circuit design have always recognized Petri nets as a powerful and easy-to-understand modelling tool. The ever-growing demand in the electronic industry for design automation to build various types of computer-based systems creates many opportunities for Petri nets to establish their role of a formal backbone in future tools for constructing systems that are increasingly becoming distributed, concurrent and asynchronous. Petri nets have already proved very effective in supporting algorithms for solving key problems in synthesis of hardware control circuits. However, since the front end to any realistic design flow in the future is likely to rely on more pragmatic Hardware Description Languages (HDLs), such as VHDL and Verilog, it is crucial that Petri nets are well interfaced to such languages. Hardware Design and Petri Nets is divided into five parts, which cover aspects of behavioral modelling, analysis and verification, synthesis from Petri nets and STGs, design environments based on high-level Petri nets and HDLs, and finally performance analysis using Petri nets. Hardware Design and Petri Nets serves as an excellent reference source and may be used as a text for advanced courses on the subject.

Synthesis of Finite State Machines: Functional Optimization is one of two monographs devoted to the synthesis of Finite State Machines (FSMs). This volume addresses functional optimization, whereas the second addresses logic optimization. By functional optimization here we mean the body of techniques that: compute all permissible sequential functions for a given topology of interconnected FSMs, and select a `best' sequential function out of the permissible ones. The result is a symbolic description of the FSM representing the chosen sequential function. By logic optimization here we mean the steps that convert a symbolic description of an FSM into a hardware implementation, with the goal to optimize objectives like area, testability, performance and so on. Synthesis of Finite State Machines: Functional Optimization is divided into three parts. The first part presents some preliminary definitions, theories and techniques related to the exploration of behaviors of FSMs. The second part presents an implicit algorithm for exact state minimization of incompletely specified finite state machines (ISFSMs), and an exhaustive presentation of explicit and implicit algorithms for the binate covering problem. The third part addresses the computation of permissible behaviors at a node of a network of FSMs and the related minimization problems of non-deterministic finite state machines (NDFSMs). Key themes running through the book are the exploration of behaviors contained in a non-deterministic FSM (NDFSM), and the representation of combinatorial problems arising in FSM synthesis by means of Binary Decision Diagrams (BDDs). Synthesis of Finite State Machines: Functional Optimization will be of interest to researchers and designers in logic synthesis, CAD and design automation.

High-Level Synthesis for Real-Time Digital Signal Processing is a comprehensive reference work for researchers and practicing ASIC design engineers. It focuses on methods for compiling complex, low to medium throughput DSP system, and on the implementation of these methods in the CATHEDRAL-II compiler. The emergence of independent silicon foundries, the reduced price of silicon real estate and the shortened processing turn-around time bring silicon technology within reach of system houses. Even for low volumes, digital systems on application-specific integrated circuits (ASICs) are becoming an economically meaningful alternative for traditional boards with analogue and digital commodity chips. ASICs cover the application region where inefficiencies inherent to general-purpose components cannot be tolerated. However, full-custom handcrafted ASIC design is often not affordable in this competitive market. Long design times, a high development cost for a low production volume, the lack of silicon designers and the lack of suited design facilities are inherent difficulties to manual full-custom chip design. To overcome these drawbacks, complex systems have to be integrated in ASICs much faster and without losing too much efficiency in silicon area and operation speed compared to handcrafted chips. The gap between system design and silicon design can only be bridged by new design (CAD). The idea of a silicon compiler, translating a behavioural system specification directly into silicon, was born from the awareness that the ability to fabricate chips is indeed outrunning the ability to design them. At this moment, CAD is one order of magnitude behind schedule. Conceptual CAD is the keyword to mastering the design complexity in ASIC design and the topic of this book.

A critical step in the design of a DSP system is to identify for each of its components (DSP kernels) an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. The book covers the entire solution space comprising both hardware multiplier-based and multiplex-less architectures that offer varying degrees of programmability. For each of the implementation styles, several algorithmic and architectural transformations are proposed so as to optimally implement weighted-sum based DSP kernels over the area-display-power space. VLSI Synthesis of DSP Kernels presents the following: Six different target implementation styles - Programmable DSP-based implementation; Programmable processors with no dedicated hardware multiplier; Implementation using hardware multiplier(s) and adder(s); Distributed Arithmetic (DA)-based implementation; Residue Number System (RNS)-based implementation; and Multiplier-less implementation (using adders and shifters) for fixed coefficient DSP kernels. For each of the implementation styles, description and analysis of several algorithmic and architectural transformations aimed at one or more of reduced area, higher performance and low power; Automated and semi-automated techniques for applying each of these transformations; and Classification of the transformations based on the properties that they exploit and their encapsulation in a design framework. A methodology that uses the framework to systematically explore the application of these transformations depending on the characteristics of the algorithm and the target implementation style. VLSI Synthesis of DSP Kernels is essential reading for designers of both hardware- and software-based DSP systems, developers of IP modules for DSP applications, EDA tools developers, researchers and managers interested in getting a comprehensive overview of current trends and future challenges in optimal implementations of DSP kernels. It will also be suitable for graduate students specialising in the area of VLSI Digital Signal Processing.

This book contains selected contributions from the 6th CIRP International Seminar on Computer-Aided Tolerancing, which was held on 22-24 March, 1999, at the University of Twente, Enschede, The Netherlands. This volume presents the theory and application of consistent tolerancing. Until recently CADCAM systems did not even address the issue of tolerances and focused purely on nominal geometry. Therefore, CAD data was only of limited use for the downstream processes. The latest generation of CADCAM systems incorporates functionality for tolerance specification. However, the lack of consistency in existing tolerancing standards and everyday tolerancing practice still lead to ill-defined products, excessive manufacturing costs and unexpected failures. Research and improvement of education in tolerancing are hot items today. Global Consistency of Tolerances gives an excellent overview of the recent developments in the field of Computer-Aided Tolerancing, including such topics as tolerance specification; tolerance analysis; tolerance synthesis; tolerance representation; geometric product specification; functional product analysis; statistical tolerancing; education of tolerancing; computational metrology; tolerancing standards; and industrial applications and CAT systems. This book is well suited to users of new generation CADCAM systems who want to use the available tolerancing possibilities properly. It can also be used as a starting point for research activities.

This book provides a solid and uniform derivation of the various properties Bezier and B-spline representations have, and shows the beauty of the underlying rich mathematical structure. The book focuses on the core concepts of Computer Aided Geometric Design and provides a clear and illustrative presentation of the basic principles, as well as a treatment of advanced material including multivariate splines, some subdivision techniques and constructions of free form surfaces with arbitrary smoothness. The text is beautifully illustrated with many excellent figures to emphasize the geometric constructive approach of this book.

Design is a fundamental creative human activity. This certainly applies to the design of artefacts, the realisation of which has to meet many constraints and ever raising criteria. The world in which we live today, is enormously influenced by the human race. Over the last century, these artefacts have dramatically changed the living conditions of humans. The present wealth in very large parts of the world, depends on it. All the ideas for better and new artefacts brought forward by humans have gone through the minds of designers, who have turned them into feasible concepts and subsequently transformed them into realistic product models. The designers have been, still are, and will remain the leading 'change agents' in the physical world. Manufacturability of artefacts has always played a significant role in design. In pre industrial manufacturing, the blacksmith held the many design and realisation aspects of a product in one hand. The synthesis of the design and manufacturing aspects took, almost implicitly, place in the head of the man. All the knowledge and the skills were stored in one person. Education and training took place along the line of many years of apprenticeship. When the production volumes increased, -'assembling to measure' was no longer tolerated and production efficiency became essential - design, process planning, production planning and fabrication became separated concerns. The designers created their own world, separated from the production world. They argued that restrictions in the freedom of designing would badly influence their creativity in design."

Electronic Chips & Systems Design Languagesoutlines and describes the latest advances in design languages. The challenge of System on a Chip (SOC) design requires designers to work in a multi-lingual environment which is becoming increasingly difficult to master. It is therefore crucial for them to learn, almost in real time, from the experiences of their colleagues in the use of design languages and how these languages have become more advanced to cope with system design. System designers, as well as students willing to become system designers, often do not have the time to attend all scientific events where they could learn the necessary information. This book will bring them a selected digest of the best contributions and industry strength case studies. All the levels of abstraction that are relevant, from the informal user requirements down to the implementation specifications, are addressed by different contributors. The author, together with colleague authors who provide valuable additional experience, presents examples of actual industrial world applications. Furthermore the academic concepts presented in this book provide excellent theories to student readers and the concepts described are up to date and in so doing provide most suitable root information for Ph.D. postgraduates.

Rapid Prototyping of Application Specific Signal Processors presents leading-edge research that focuses on design methodology, infrastructure support and scalable architectures developed by the 150 million dollar DARPA United States Department of Defense RASSP Program. The contributions to this edited work include an introductory overview chapter that explains the origin, concepts and status of this effort. The RASSP Program is a multi-year DARPA/Tri-Service initiative intended to dramatically improve the process by which complex digital systems, particularly embedded signal processors, are designed, manufactured, upgraded and supported. This program was originally driven by military applications for signal processing. The requirements of military applications for real-time signal processing are typically more demanding than those of commercial applications, but the time gap between technology employed in advanced military prototypes and commercial products is narrowing rapidly. The research on methodologies, infrastructure and architectures presented in this book is applicable to commercial signal processing systems that are in design now, or will be developed before the end of the decade. Rapid Prototyping of Application Specific Signal Processors is a valuable reference for developers of embedded digital systems, particularly systems engineers for signal processing systems (such as digital TV, biomedical image processing systems and telecommunications) and for military contractors who are developing signal processing systems. This book will also be of interest to managers who are charged with responsibility for creating and maintaining environments and infrastructures for developing large embedded digital systems. The chief value for managers will be the defining of methods and processes that reduce development time and cost.

With the advent of portable and autonomous computing systems, power con sumption has emerged as a focal point in many research projects, commercial systems and DoD platforms. One current research initiative, which drew much attention to this area, is the Power Aware Computing and Communications (PAC/C) program sponsored by DARPA. Many of the chapters in this book include results from work that have been supported by the PACIC program. The performance of computer systems has been tremendously improving while the size and weight of such systems has been constantly shrinking. The capacities of batteries relative to their sizes and weights has been also improv ing but at a rate which is much slower than the rate of improvement in computer performance and the rate of shrinking in computer sizes. The relation between the power consumption of a computer system and it performance and size is a complex one which is very much dependent on the specific system and the technology used to build that system. We do not need a complex argument, however, to be convinced that energy and power, which is the rate of energy consumption, are becoming critical components in computer systems in gen eral, and portable and autonomous systems, in particular. Most of the early research on power consumption in computer systems ad dressed the issue of minimizing power in a given platform, which usually translates into minimizing energy consumption, and thus, longer battery life."

Behavioral Intervals in Embedded Software introduces a comprehensive approach to timing, power, and communication analysis of embedded software processes. Embedded software timing, power and communication are typically not unique but occur in intervals which result from data dependent behavior, environment timing and target system properties.
In system design, these intervals are used in many ways. In some cases, only the worst case is of interest, e.g. for single processor schedulability analysis, in another context both best and worst cases are relevant, such as for multiprocessor scheduling. In all these cases, these behavioral intervals of the individual software processes are fundamental data needed to analyze system behavior. With growing importance of embedded software, formal analysis of behavioral intervals has met increasing interest. Major contributions were the introduction of implicit path enumeration and the inclusion of cache analysis. While all approaches are conservative, i.e. all possible timing behavior (or communication, power consumption) is included in the resulting intervals, the main differences are in the architecture features that are covered by the hardware model and the width of the conservative interval. The closer this interval to the real timing bounds, the higher is the practical use of formal analysis.
The current analysis techniques leverage on previous work in compiler technology by using basic blocks as elementary units for architecture modeling and path analysis. The work presented here opens a new direction moving from basic block based analysis to an analysis based on larger program segments with a single execution path. Such program segments frequently extend over many basic blocks, in particular in embedded system applications.
The approach combines the generality and accuracy of formal analysis with the modeling precision of cycle true simulation without compromising formal completeness. The results show that with this combination of tracing and formal analysis both higher precision than previous approaches leading to tighter and more realistic intervals can be obtained and easier adaptation due to the use of standard off-the-shelf cache simulators, cycle-true processor models or evaluation boards is possible.
Behavioral Intervals in Embedded Software will be a useful reference for academics as well as research scientists who are active in the field of Design Automation and Embedded Systems.

For someone with a hammer the whole world looks like a nail. Within the last 10-13 years Binar.y Decision Diagmms (BDDs) have become the state-of-the-art data structure in VLSI CAD for representation and ma nipulation of Boolean functions. Today, BDDs are widely used and in the meantime have also been integrated in commercial tools, especially in the area of verijication and synthesis. The interest in BDDs results from the fact that the data structure is generally accepted as providing a good compromise between conciseness of representation and efficiency of manipulation. With increasing number of applications, also in non CAD areas, classical methods to handle BDDs are being improved and new questions and problems evolve and have to be solved. The book should help the reader who is not familiar with BDDs (or DDs in general) to get a quick start. On the other hand it will discuss several new aspects of BDDs, e.g. with respect to minimization and implementation of a package. This will help people working with BDDs (in industry or academia) to keep informed about recent developments in this area."

Reasoning in Boolean Networks provides a detailed treatment of recent research advances in algorithmic techniques for logic synthesis, test generation and formal verification of digital circuits. The book presents the central idea of approaching design automation problems for logic-level circuits by specific Boolean reasoning techniques. While Boolean reasoning techniques have been a central element of two-level circuit theory for many decades Reasoning in Boolean Networks describes a basic reasoning methodology for multi-level circuits. This leads to a unified view on two-level and multi-level logic synthesis. The presented reasoning techniques are applied to various CAD-problems to demonstrate their usefulness for today's industrially relevant problems. Reasoning in Boolean Networks provides lucid descriptions of basic algorithmic concepts in automatic test pattern generation, logic synthesis and verification and elaborates their intimate relationship to provide further intuition and insight into the subject. Numerous examples are provide for ease in understanding the material. Reasoning in Boolean Networks is intended for researchers in logic synthesis, VLSI testing and formal verification as well as for integrated circuit designers who want to enhance their understanding of basic CAD methodologies.

Johan H. Huijsing This book contains 18 tutorial papers concentrated on 3 topics, each topic being covered by 6 papers. The topics are: Low-Noise, Low-Power, Low-Voltage Mixed-Mode Design with CAD Tools Voltage, Current, and Time References The papers of this book were written by top experts in the field, currently working at leading European and American universities and companies. These papers are the reviewed versions of the papers presented at the Workshop on Advances in Analog Circuit Design. which was held in Villach, Austria, 26-28 April 1995. The chairman of the Workshop was Dr. Franz Dielacher from Siemens, Austria. The program committee existed of Johan H. Huijsing from the Delft University of Technology, Prof.Willy Sansen from the Catholic University of Leuven, and Dr. Rudy 1. van der Plassche from Philips Eindhoven. This book is the fourth of aseries dedicated to the design of analog circuits. The topics which were covered earlier were: Operational Amplifiers Analog to Digital Converters Analog Computer Aided Design Mixed AlD Circuit Design Sensor Interface Circuits Communication Circuits Low-Power, Low-Voltage Integrated Filters Smart Power As the Workshop will be continued year by year, a valuable series of topics will be built up from all the important areas of analog circuit design. I hope that this book will help designers of analog circuits to improve their work and to speed it up.

It is well known that embedded systems have to be implemented efficiently. This requires that processors optimized for certain application domains are used in embedded systems. Such an optimization requires a careful exploration of the design space, including a detailed study of cost/performance tradeoffs. In order to avoid time-consuming assembly language programming during design space exploration, compilers are needed. In order to analyze the effect of various software or hardware configurations on the performance, retargetable compilers are needed that can generate code for numerous different potential hardware configurations. This book provides a comprehensive and up-to-date overview of the fast developing area of retargetable compilers for embedded systems. It describes a large set important tools as well as applications of retargetable compilers at different levels in the design flow. Retargetable Compiler Technology for Embedded Systems is mostly self-contained and requires only fundamental knowledge in software and compiler design. It is intended to be a key reference for researchers and designers working on software, compilers, and processor optimization for embedded systems.

"CAAD Futures" is a bi-annual conference that aims to promote the advancement of computer-aided architectural design in the service of those concerned with the quality of the built environment. The conferences are organized under the auspices of the CAAD Futures Foundation, which has its secretariat at the Eindhoven University of Technology in the Netherlands.

This book contains papers prepared for the 10th CAAD Futures conference that took place at the National Cheng Kung University, 28 to 30 April, 2003. The chapters provide an overview of the state-of-the-art in research on computer-aided architectural design at that time. Information on the CAAD Futures Foundation and its conferences can be found at http: //www.caadfutures.arch.tue.nl

In VLSI CAD, difficult optimization problems have to be solved on a constant basis. Various optimization techniques have been proposed in the past. While some of these methods have been shown to work well in applications and have become somewhat established over the years, other techniques have been ignored. Recently, there has been a growing interest in optimization algorithms based on principles observed in nature, termed Evolutionary Algorithms (EAs). Evolutionary Algorithms in VLSI CAD presents the basic concepts of EAs, and considers the application of EAs in VLSI CAD. It is the first book to show how EAs could be used to improve IC design tools and processes. Several successful applications from different areas of circuit design, like logic synthesis, mapping and testing, are described in detail. Evolutionary Algorithms in VLSI CAD consists of two parts. The first part discusses basic principles of EAs and provides some easy-to-understand examples. Furthermore, a theoretical model for multi-objective optimization is presented. In the second part a software implementation of EAs is supplied together with detailed descriptions of several EA applications. These applications cover a wide range of VLSI CAD, and different methods for using EAs are described. Evolutionary Algorithms in VLSI CAD is intended for CAD developers and researchers as well as those working in evolutionary algorithms and techniques supporting modern design tools and processes.

A major advantage of a direct digital synthesizer is that its output frequency, phase and amplitude can be precisely and rapidly manipulated under digital processor control. This book was written to find possible applications for radio communication systems.

During the last few years Field Programmable Gate Arrays (FPGAs) have become increasingly important. Thanks to recent breakthroughs in technology, FPGAs offer millions of system gates at low cost and considerable speed. Functional decomposition has emerged as an essential technique in automatic logic synthesis for FPGAs. Functional decomposition as a technique to find realizations for Boolean functions was already introduced in the late fifties and early sixties by Ashenhurst, Curtis, Roth and Karp. In recent years, however, it has attracted a great deal of renewed attention, for several reasons. First, it is especially well suited for the synthesis of lookup-table based FPGAs. Also, the increased capacities of today's computers as well as the development of new methods have made the method applicable to larger-scale problems. Modern techniques for functional decomposition profit from the success of Reduced Ordered Binary Decision Diagrams (ROBDDs), data structures that provide compact representations for many Boolean functions occurring in practical applications. We have now seen the development of algorithms for functional decomposition which work directly based on ROBDDs, so that the decomposition algorithm works based on compact representations and not on function tables or decomposition matrices as in previous approaches. The book presents, in a consistent manner, a comprehensive presentation of a multitude of results stemming from the author's as well as various researchers' work in the field. Apart from the basic method, it also covers functional decomposition for incompletely specified functions, decomposition for multi-output functions and non-disjoint decomposition. Functional Decomposition with Application to FPGA Synthesis will be of interest both to researchers and advanced students in logic synthesis, VLSI CAD, and Design Automation as well as professionals working in FPGA design and the development of algorithms for FPGA synthesis.

Today more than 90% of all programmable processors are employed in embedded systems. This number is actually not surprising, contemplating that in a typical home you might find one or two PCs equipped with high-performance standard processors, and probably dozens of embedded systems, including electronic entertainment, household, and telecom devices, each of them equipped with one or more embedded processors. The question arises why programmable processors are so popular in embedded system design. The answer lies in the fact that they help to narrow the gap between chip capacity and designer productivity. Embedded processors cores are nothing but one step further towards improved design reuse, just along the lines of standard cells in logic synthesis and macrocells in RTL synthesis in earlier times of IC design. Additionally, programmable processors permit to migrate functionality from hardware to software, resulting in an even improved reuse factor as well as greatly increased flexibility.

The LISA processor design platform (LPDP) presented in Architecture Exploration for Embedded Processors with LISA addresses recent design challenges and results in highly satisfactory solutions. The LPDP covers all major high-level phases of embedded processor design and is capable of automatically generating almost all required software development tools from processor models in the LISA language. It supports a profiling-based, stepwise refinement of processor models down to cycle-accurate and even RTL synthesis models. Moreover, it elegantly avoids model inconsistencies otherwise omnipresent in traditional design flows.

The next step in design reuse is already in sight: SoC platforms, i.e., partially pre-designed multi-processor templates that can be quickly tuned towards given applications thereby guaranteeing a high degree of hardware/software reuse in system-level design. Consequently, the LPDP approach goes even beyond processor architecture design. The LPDP solution explicitly addresses SoC integration issues by offering comfortable APIs for external simulation environments as well as clever solutions for the problem of both efficient and user-friendly heterogeneous multiprocessor debugging.