Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.

Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.

Behavioral Intervals in Embedded Software introduces a comprehensive approach to timing, power, and communication analysis of embedded software processes. Embedded software timing, power and communication are typically not unique but occur in intervals which result from data dependent behavior, environment timing and target system properties.
In system design, these intervals are used in many ways. In some cases, only the worst case is of interest, e.g. for single processor schedulability analysis, in another context both best and worst cases are relevant, such as for multiprocessor scheduling. In all these cases, these behavioral intervals of the individual software processes are fundamental data needed to analyze system behavior. With growing importance of embedded software, formal analysis of behavioral intervals has met increasing interest. Major contributions were the introduction of implicit path enumeration and the inclusion of cache analysis. While all approaches are conservative, i.e. all possible timing behavior (or communication, power consumption) is included in the resulting intervals, the main differences are in the architecture features that are covered by the hardware model and the width of the conservative interval. The closer this interval to the real timing bounds, the higher is the practical use of formal analysis.
The current analysis techniques leverage on previous work in compiler technology by using basic blocks as elementary units for architecture modeling and path analysis. The work presented here opens a new direction moving from basic block based analysis to an analysis based on larger program segments with a single execution path. Such program segments frequently extend over many basic blocks, in particular in embedded system applications.
The approach combines the generality and accuracy of formal analysis with the modeling precision of cycle true simulation without compromising formal completeness. The results show that with this combination of tracing and formal analysis both higher precision than previous approaches leading to tighter and more realistic intervals can be obtained and easier adaptation due to the use of standard off-the-shelf cache simulators, cycle-true processor models or evaluation boards is possible.
Behavioral Intervals in Embedded Software will be a useful reference for academics as well as research scientists who are active in the field of Design Automation and Embedded Systems.

This book provides a solid and uniform derivation of the various properties Bezier and B-spline representations have, and shows the beauty of the underlying rich mathematical structure. The book focuses on the core concepts of Computer Aided Geometric Design and provides a clear and illustrative presentation of the basic principles, as well as a treatment of advanced material including multivariate splines, some subdivision techniques and constructions of free form surfaces with arbitrary smoothness. The text is beautifully illustrated with many excellent figures to emphasize the geometric constructive approach of this book.

High-Level Synthesis for Real-Time Digital Signal Processing is a comprehensive reference work for researchers and practicing ASIC design engineers. It focuses on methods for compiling complex, low to medium throughput DSP system, and on the implementation of these methods in the CATHEDRAL-II compiler. The emergence of independent silicon foundries, the reduced price of silicon real estate and the shortened processing turn-around time bring silicon technology within reach of system houses. Even for low volumes, digital systems on application-specific integrated circuits (ASICs) are becoming an economically meaningful alternative for traditional boards with analogue and digital commodity chips. ASICs cover the application region where inefficiencies inherent to general-purpose components cannot be tolerated. However, full-custom handcrafted ASIC design is often not affordable in this competitive market. Long design times, a high development cost for a low production volume, the lack of silicon designers and the lack of suited design facilities are inherent difficulties to manual full-custom chip design. To overcome these drawbacks, complex systems have to be integrated in ASICs much faster and without losing too much efficiency in silicon area and operation speed compared to handcrafted chips. The gap between system design and silicon design can only be bridged by new design (CAD). The idea of a silicon compiler, translating a behavioural system specification directly into silicon, was born from the awareness that the ability to fabricate chips is indeed outrunning the ability to design them. At this moment, CAD is one order of magnitude behind schedule. Conceptual CAD is the keyword to mastering the design complexity in ASIC design and the topic of this book.

A critical step in the design of a DSP system is to identify for each of its components (DSP kernels) an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. The book covers the entire solution space comprising both hardware multiplier-based and multiplex-less architectures that offer varying degrees of programmability. For each of the implementation styles, several algorithmic and architectural transformations are proposed so as to optimally implement weighted-sum based DSP kernels over the area-display-power space. VLSI Synthesis of DSP Kernels presents the following: Six different target implementation styles - Programmable DSP-based implementation; Programmable processors with no dedicated hardware multiplier; Implementation using hardware multiplier(s) and adder(s); Distributed Arithmetic (DA)-based implementation; Residue Number System (RNS)-based implementation; and Multiplier-less implementation (using adders and shifters) for fixed coefficient DSP kernels. For each of the implementation styles, description and analysis of several algorithmic and architectural transformations aimed at one or more of reduced area, higher performance and low power; Automated and semi-automated techniques for applying each of these transformations; and Classification of the transformations based on the properties that they exploit and their encapsulation in a design framework. A methodology that uses the framework to systematically explore the application of these transformations depending on the characteristics of the algorithm and the target implementation style. VLSI Synthesis of DSP Kernels is essential reading for designers of both hardware- and software-based DSP systems, developers of IP modules for DSP applications, EDA tools developers, researchers and managers interested in getting a comprehensive overview of current trends and future challenges in optimal implementations of DSP kernels. It will also be suitable for graduate students specialising in the area of VLSI Digital Signal Processing.

Hierarchical design methods were originally introduced for the design of digital ICs, and they appeared to provide for significant advances in design productivity, Time-to-Market, and first-time right design. These concepts have gained increasing importance in the semiconductor industry in recent years. In the course of time, the supportive quality of hierarchical methods and their advantages were confirmed. System Level Hardware/Software Co-design: An Industrial Approach demonstrates the applicability of hierarchical methods to hardware / software codesign, and mixed analogue / digital design following a similar approach. Hierarchical design methods provide for high levels of design support, both in a qualitative and a quantitative sense. In the qualitative sense, the presented methods support all phases in the product life cycle of electronic products, ranging from requirements analysis to application support. Hierarchical methods furthermore allow for efficient digital hardware design, hardware / software codesign, and mixed analogue / digital design, on the basis of commercially available formalisms and design tools. In the quantitative sense, hierarchical methods have prompted a substantial increase in design productivity. System Level Hardware/Software Co-design: An Industrial Approach reports on a six year study during which time the number of square millimeters of normalized complexity an individual designer contributed every week rose by more than a factor of five. Hierarchical methods therefore enabled designers to keep track of the ever increasing design complexity, while effectively reducing the number of design iterations in the form of redesigns. System Level Hardware/Software Co-design: An Industrial Approach is the first book to provide a comprehensive, coherent system design methodology that has been proven to increase productivity in industrial practice. The book will be of interest to all managers, designers and researchers working in the semiconductor industry.

Design is a fundamental creative human activity. This certainly applies to the design of artefacts, the realisation of which has to meet many constraints and ever raising criteria. The world in which we live today, is enormously influenced by the human race. Over the last century, these artefacts have dramatically changed the living conditions of humans. The present wealth in very large parts of the world, depends on it. All the ideas for better and new artefacts brought forward by humans have gone through the minds of designers, who have turned them into feasible concepts and subsequently transformed them into realistic product models. The designers have been, still are, and will remain the leading 'change agents' in the physical world. Manufacturability of artefacts has always played a significant role in design. In pre industrial manufacturing, the blacksmith held the many design and realisation aspects of a product in one hand. The synthesis of the design and manufacturing aspects took, almost implicitly, place in the head of the man. All the knowledge and the skills were stored in one person. Education and training took place along the line of many years of apprenticeship. When the production volumes increased, -'assembling to measure' was no longer tolerated and production efficiency became essential - design, process planning, production planning and fabrication became separated concerns. The designers created their own world, separated from the production world. They argued that restrictions in the freedom of designing would badly influence their creativity in design."

Electronic Chips & Systems Design Languagesoutlines and describes the latest advances in design languages. The challenge of System on a Chip (SOC) design requires designers to work in a multi-lingual environment which is becoming increasingly difficult to master. It is therefore crucial for them to learn, almost in real time, from the experiences of their colleagues in the use of design languages and how these languages have become more advanced to cope with system design. System designers, as well as students willing to become system designers, often do not have the time to attend all scientific events where they could learn the necessary information. This book will bring them a selected digest of the best contributions and industry strength case studies. All the levels of abstraction that are relevant, from the informal user requirements down to the implementation specifications, are addressed by different contributors. The author, together with colleague authors who provide valuable additional experience, presents examples of actual industrial world applications. Furthermore the academic concepts presented in this book provide excellent theories to student readers and the concepts described are up to date and in so doing provide most suitable root information for Ph.D. postgraduates.

Today more than 90% of all programmable processors are employed in embedded systems. This number is actually not surprising, contemplating that in a typical home you might find one or two PCs equipped with high-performance standard processors, and probably dozens of embedded systems, including electronic entertainment, household, and telecom devices, each of them equipped with one or more embedded processors. The question arises why programmable processors are so popular in embedded system design. The answer lies in the fact that they help to narrow the gap between chip capacity and designer productivity. Embedded processors cores are nothing but one step further towards improved design reuse, just along the lines of standard cells in logic synthesis and macrocells in RTL synthesis in earlier times of IC design. Additionally, programmable processors permit to migrate functionality from hardware to software, resulting in an even improved reuse factor as well as greatly increased flexibility.

The LISA processor design platform (LPDP) presented in Architecture Exploration for Embedded Processors with LISA addresses recent design challenges and results in highly satisfactory solutions. The LPDP covers all major high-level phases of embedded processor design and is capable of automatically generating almost all required software development tools from processor models in the LISA language. It supports a profiling-based, stepwise refinement of processor models down to cycle-accurate and even RTL synthesis models. Moreover, it elegantly avoids model inconsistencies otherwise omnipresent in traditional design flows.

The next step in design reuse is already in sight: SoC platforms, i.e., partially pre-designed multi-processor templates that can be quickly tuned towards given applications thereby guaranteeing a high degree of hardware/software reuse in system-level design. Consequently, the LPDP approach goes even beyond processor architecture design. The LPDP solution explicitly addresses SoC integration issues by offering comfortable APIs for external simulation environments as well as clever solutions for the problem of both efficient and user-friendly heterogeneous multiprocessor debugging.

During the last few years Field Programmable Gate Arrays (FPGAs) have become increasingly important. Thanks to recent breakthroughs in technology, FPGAs offer millions of system gates at low cost and considerable speed. Functional decomposition has emerged as an essential technique in automatic logic synthesis for FPGAs. Functional decomposition as a technique to find realizations for Boolean functions was already introduced in the late fifties and early sixties by Ashenhurst, Curtis, Roth and Karp. In recent years, however, it has attracted a great deal of renewed attention, for several reasons. First, it is especially well suited for the synthesis of lookup-table based FPGAs. Also, the increased capacities of today's computers as well as the development of new methods have made the method applicable to larger-scale problems. Modern techniques for functional decomposition profit from the success of Reduced Ordered Binary Decision Diagrams (ROBDDs), data structures that provide compact representations for many Boolean functions occurring in practical applications. We have now seen the development of algorithms for functional decomposition which work directly based on ROBDDs, so that the decomposition algorithm works based on compact representations and not on function tables or decomposition matrices as in previous approaches. The book presents, in a consistent manner, a comprehensive presentation of a multitude of results stemming from the author's as well as various researchers' work in the field. Apart from the basic method, it also covers functional decomposition for incompletely specified functions, decomposition for multi-output functions and non-disjoint decomposition. Functional Decomposition with Application to FPGA Synthesis will be of interest both to researchers and advanced students in logic synthesis, VLSI CAD, and Design Automation as well as professionals working in FPGA design and the development of algorithms for FPGA synthesis.

This new book on Analog Circuit Design contains the revised contributions of all the tutorial speakers of the eight workshop AACD (Advances in Analog Circuit Design), which was held at Nice, France on March 23-25, 1999. The workshop was organized by Yves Leduc of TI Nice, France. The program committee consisted of Willy Sansen, K.U.Leuven, Belgium, Han Huijsing, T.U.Delft, The Netherlands and Rudy van de Plassche, T.U.Eindhoven, The Netherlands. The aim of these AACD workshops is to bring together a restricted group of about 100 people who are personally advancing the frontiers of analog circuit design to brainstorm on new possibilities and future developments in a restricted number of fields. They are concentrated around three topics. In each topic six speakers give a tutorial presentation. Eighteen papers are thus included in this book. The topics of 1999 are: (X)DSL and other communication systems RF MOST models Integrated filters and oscillators The other topics, which have been coverd before, are: 1992 Operational amplifiers A-D Converters Analog CAD 1993 Mixed-mode A]D design Sensor interfaces Communication circuits 1994 Low-power low-voltage design Integrated filters Smart power 1995 Low-noise low-power low-voltge design Mixed-mode design with CAD tools Voltage, current and time references vii viii 1996 RF CMOS circuit design Bandpass sigma-delta and other data converters Translinear circuits 1997 RF A-D Converters Sensor and actuator interfaces Low-noise oscillators, PLL's and synthesizers 1998 I-Volt electronics Design and implementation of mixed-mode systems Low-noise amplifiers and RF power amplifiers for telecommunications

Our society is faced with an increasing dependence on computing systems, not only in high tech consumer applications but also in areas (e.g., air and railway traffic control, nuclear plant control, aircraft and car control) where a failure can be critical for the safety of human beings. Unfortunately, it is accepted that large digital systems cannot be fault-free. Some faults may be attributed to inaccuracy during the development, while others can come from external causes such as environmental stress. Radiations, electromagnetic interference and power glitches are some of the most common causes of transient faults.
As a consequence, the past years have seen a growing interest in methods for studying the behaviour of computer-based systems when faults occur, and several approaches have been proposed to evaluate the dependability properties of a computer-based system.
Fault Injection, i.e., the artificial injection of faults into a computer system in order to study its behaviour, emerged as a viable solution, and has been deeply investigated by both academia and industry. Different techniques have been proposed and some of them practically experimented.
Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation intends to be a comprehensive guide to Fault Injection techniques used to evaluate the dependability of a digital system. The description and the critical analysis of different Fault Injection techniques and tools will be authored by key scientists in the field of system dependability and fault tolerance.

Test functions (fault detection, diagnosis, error correction, repair, etc.) that are applied concurrently while the system continues its intended function are defined as on-line testing. In its expanded scope, on-line testing includes the design of concurrent error checking subsystems that can be themselves self-checking, fail-safe systems that continue to function correctly even after an error occurs, reliability monitoring, and self-test and fault-tolerant designs. On-Line Testing for VLSI contains a selected set of articles that discuss many of the modern aspects of on-line testing as faced today. The contributions are largely derived from recent IEEE International On-Line Testing Workshops. Guest editors Michael Nicolaidis, Yervant Zorian and Dhiraj Pradhan organized the articles into six chapters. In the first chapter the editors introduce a large number of approaches with an expanded bibliography in which some references date back to the sixties. On-Line Testing for VLSI is an edited volume of original research comprising invited contributions by leading researchers.

System-on-Chip Methodologies & Design Languages brings together a selection of the best papers from three international electronic design language conferences in 2000. The conferences are the Hardware Description Language Conference and Exhibition (HDLCon), held in the Silicon Valley area of USA; the Forum on Design Languages (FDL), held in Europe; and the Asia Pacific Chip Design Language (APChDL) Conference. The papers cover a range of topics, including design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The results presented in these papers will help researchers and practicing engineers keep abreast of developments in this rapidly evolving field.

From the Foreword..... Modern digital signal processing applications provide a large challenge to the system designer. Algorithms are becoming increasingly complex, and yet they must be realized with tight performance constraints. Nevertheless, these DSP algorithms are often built from many constituent canonical subtasks (e.g., IIR and FIR filters, FFTs) that can be reused in other subtasks. Design is then a problem of composing these core entities into a cohesive whole to provide both the intended functionality and the required performance. In order to organize the design process, there have been two major approaches. The top-down approach starts with an abstract, concise, functional description which can be quickly generated. On the other hand, the bottom-up approach starts from a detailed low-level design where performance can be directly assessed, but where the requisite design and interface detail take a long time to generate. In this book, the authors show a way to effectively resolve this tension by retaining the high-level conciseness of VHDL while parameterizing it to get good fit to specific applications through reuse of core library components. Since they build on a pre-designed set of core elements, accurate area, speed and power estimates can be percolated to high- level design routines which explore the design space. Results are impressive, and the cost model provided will prove to be very useful. Overall, the authors have provided an up-to-date approach, doing a good job at getting performance out of high-level design. The methodology provided makes good use of extant design tools, and is realistic in terms of the industrial design process. The approach is interesting in its own right, but is also of direct utility, and it will give the existing DSP CAD tools a highly competitive alternative. The techniques described have been developed within ARPAs RASSP (Rapid Prototyping of Application Specific Signal Processors) project, and should be of great interest there, as well as to many industrial designers. Professor Jonathan Allen, Massachusetts Institute of Technology

Today, Fuzzy Set Theory is the core discipline of so-called soft computing, and provides new impetus for research in the field of artificial intelligence. In this fascinating book, the history of Fuzzy Set Theory and the ways it was first used are incorporated into the history of 20th century science and technology. Influences from philosophy, system theory and cybernetics stemming from the earliest part of the 20th century are considered alongside those of communication and control theory from mid-century.

This book aims at providing a view of the current trends in the development of research on Synthesis and Control of Discrete Event Systems. Papers col lected in this volume are based on a selection of talks given in June and July 2001 at two independent meetings: the Workshop on Synthesis of Concurrent Systems, held in Newcastle upon Tyne as a satellite event of ICATPN/ICACSD and organized by Ph. Darondeau and L. Lavagno, and the Symposium on the Supervisory Control of Discrete Event Systems (SCODES), held in Paris as a satellite event of CAV and organized by B. Caillaud and X. Xie. Synthesis is a generic term that covers all procedures aiming to construct from specifications given as input objects matching these specifications. The ories and applications of synthesis have been studied and developped for long in connection with logics, programming, automata, discrete event systems, and hardware circuits. Logics and programming are outside the scope of this book, whose focus is on Discrete Event Systems and Supervisory Control. The stress today in this field is on a better applicability of theories and algorithms to prac tical systems design. Coping with decentralization or distribution and caring for an efficient realization of the synthesized systems or controllers are of the utmost importance in areas so diverse as the supervision of embedded or man ufacturing systems, or the implementation of protocols in software or in hard ware."

Web Personalization can be de?ned as any set of actions that can tailor the Webexperiencetoaparticularuserorsetofusers. Toachievee?ectivepers- alization, organizationsmustrelyonallavailabledata, includingtheusageand click-stream data (re?ecting user behaviour), the site content, the site str- ture, domainknowledge, aswellasuserdemographicsandpro?les. Inaddition, e?cient and intelligent techniques are needed to mine this data for actionable knowledge, and to e?ectively use the discovered knowledge to enhance the users' Web experience. These techniques must address important challenges emanating from the size and the heterogeneous nature of the data itself, as wellasthedynamicnatureofuserinteractionswiththeWeb. Thesechallenges include the scalability of the personalization solutions, data integration, and successful integration of techniques from machine learning, information - trievaland?ltering, databases, agentarchitectures, knowledgerepresentation, data mining, text mining, statistics, user modelling and human-computer - teraction. The Semantic Web adds one more dimension to this. The workshop will focus on the semantic web approach to personalization and adaptation. The Web has been formed to be an integral part of numerous applications inwhichauserinteractswithaserviceprovider, productsellers, governmental organisations, friends and colleagues. Content and services are available at di?erent sources and places. Hence, Web applications need to combine all available knowledge in order to form personalized, user-friendly, and busine- optimal servi

Power consumption is a key limitation in many high-speed and high-data-rate electronic systems today, ranging from mobile telecom to portable and desktop computing systems, especially when moving to nanometer technologies. Ultra Low-Power Electronics and Design offers to the reader the unique opportunity of accessing in an easy and integrated fashion a mix of tutorial material and advanced research results, contributed by leading scientists from academia and industry, covering the most hot and up-to-date issues in the field of the design of ultra low-power devices, systems and applications.

The chapters of this book summarize the lectures delivered du ring the NATO Advanced Study Institute (ASI) on Computational Methods in Mechanisms, that took place in the Sts. Constantin and Elena Resort, near Varna, on the Bulgarian Coast of the Black Sea, June 16-28, 1997. The purpose of the ASI was to bring together leading researchers in the area of mechanical systems at large, with special emphasis in the computational issues around their analysis, synthesis, and optimization, during two weeks of lectures and discussion. A total of 89 participants from 23 count ries played an active role during the lectures and sessions of contributed papers. Many of the latter are being currently reviewed for publication in specialized journals. The subject of the book is mechanical systems, Le., systems composed of rigid and flexible bodies, coupled by mechanical means so as to constrain their various bodies in a goal-oriented manner, usually driven under computer con trol. Applications of the discipline are thus of the most varied nature, ranging from transportation systems to biomedical devices. U nder normal operation conditions, the constitutive bodies of a mechanical system can be consid ered to be rigid, the rigidity property then easing dramatically the analysis of the kinematics and dynamics of the system at hand. Examples of these systems are the suspension of a terrestrial vehicle negotiating a curve at speeds within the allowed or recommended limits and the links of multiaxis industrial robots performing conventional pick-and-place operations."

Design automation of electronic and hybrid systems is a steadily growing field of interest and a permanent challenge for researchers in Electronics, Computer Engineering and Computer Science. System Design Automation presents some recent results in design automation of different types of electronic and mechatronic systems. It deals with various topics of design automation, ranging from high level digital system synthesis, through analogue and heterogeneous system analysis and design, up to system modeling and simulation. Design automation is treated from the aspects of its theoretical fundamentals, its basic approach and its methods and tools. Several application cases are presented in detail. The book consists of three chapters: High-Level System Synthesis (Digital Hardware/Software Systems). Here embedded systems, distributed systems and processor arrays as well as hardware-software codesign are treated. Also three special application cases are discussed in detail; Analog and Heterogeneous System Design (System Approach and Methodology). This chapter copes with the analysis and design of hybrid systems comprised of analog and digital, electronic and mechanical components; System Simulation and Evaluation (Methods and Tools). In this chapter object-oriented Modelling, analog system simulation including fault-simulation, parameter optimization and system validation are regarded. The contents of the book are based on material presented at the Workshop System Design Automation (SDA 2000) organised by the Sonderforschungsbereich 358 of the Deutsche Forschungsgemeinschaft at TU Dresden.

I am honored and delighted to write the foreword to this very first book about SystemC. It is now an excellent time to summarize what SystemC really is and what it can be used for. The main message in the area of design in the 2001 International Te- nologyRoadmapfor Semiconductors (ITRS) isthat"cost ofdesign is the greatest threat to the continuation ofthe semiconductor roadmap. " This recent revision of the ITRS describes the major productivity improvements of the last few years as "small block reuse," "large block reuse ," and "IC implementation tools. " In order to continue to reduce design cost, the - quired future solutions will be "intelligent test benches" and "embedded system-level methodology. " As the new system-level specification and design language, SystemC - rectly contributes to these two solutions. These will have the biggest - pact on future design technology and will reduce system implementation cost. Ittook SystemC less than two years to emerge as the leader among the many new and well-discussed system-level designlanguages. Inmy op- ion, this is due to the fact that SystemC adopted object-oriented syst- level design-the most promising method already applied by the majority of firms during the last couple of years. Even before the introduction of SystemC, many system designers have attempted to develop executable specifications in C++. These executable functional specifications are then refined to the well-known transaction level, to model the communication of system-level processes.

This book provides a complete overview of the field of carbon nanotube electronics. It covers materials and physical properties, synthesis and fabrication processes, devices and circuits, modeling, and finally novel applications of nanotube-based electronics. The book introduces fundamental device physics and circuit concepts of 1-D electronics. At the same time it provides specific examples of the state-of-the-art nanotube devices.

The papers collected in this volume were originally presented at the conference on Design and Decision Support Systems in Architecture and Urban Planning that was held in Mierlo, the Netherlands in July 1992. This conference was organized as one of the events celebrating the 25th anniversary of the founding of the Faculty of Architecture, Building and Planning at Eindhoven University of Technology. The organizing committee had a strong feeling that many interesting developments in this area were emerging within different institutional frameworks and informal networks that do not interact frequently. For example, scholars working on architectural problems are not particularly familiar with computer applications in urban planning. Likewise, although many computer-aided design systems claim to be based on principles of design methodology, serious discussions on the methodological underpinnings of such systems are relatively scarce. Consequently, we may have little opportunity to learn how scholars in closely related disciplines approach specific design or planning problems.

The world of wireless communications is changing very rapidly since a few years. The introduction of digital data communication in combination with digital signal process ing has created the foundation for the development of many new wireless applications. High-quality digital wireless networks for voice communication with global and local coverage, like the GSM and DECT system, are only faint and early examples of the wide variety of wireless applications that will become available in the remainder of this decade. The new evolutions in wireless communications set new requirements for the trans ceivers (transmitter-receivers). Higher operating frequencies, a lower power consump tion and a very high degree of integration, are new specifications which ask for design approaches quite different from the classical RF design techniques. The integrata bility and power consumption reduction of the digital part will further improve with the continued downscaling of technologies. This is however completely different for the analog transceiver front-end, the part which performs the interfacing between the antenna and the digital signal processing. The analog front-end's integratability and power consumption are closely related to the physical limitations of the transceiver topology and not so much to the scaling of the used technology. Chapter 2 gives a detailed study of the level of integration in current transceiver realization and analyzes their limitations. In chapter 3 of this book the complex signal technique for the analysis and synthesis of multi-path receiver and transmitter topologies is introduced."