In recent years meshless/meshfree methods have gained considerable attention in engineering and applied mathematics. The variety of problems that are now being addressed by these techniques continues to expand and the quality of the results obtained demonstrates the effectiveness of many of the methods currently available. The book presents a significant sample of the state of the art in the field with methods that have reached a certain level of maturity while also addressing many open issues. The book collects extended original contributions presented at the Second ECCOMAS Conference on Meshless Methods held in 2007 in Porto. The list of contributors reveals a fortunate mix of highly distinguished authors as well as quite young but very active and promising researchers, thus giving the reader an interesting and updated view of different meshless approximation methods and their range of applications. The material presented is appropriate for researchers, engineers, physicists, applied mathematicians and graduate students interested in this active research area.

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

AND BACKGROUND 1. 1 CAD, Specification and Simulation Computer Aided Design (CAD) is today a widely used expression referring to the study of ways in which computers can be used to expedite the design process. This can include the design of physical systems, architectural environments, manufacturing processes, and many other areas. This book concentrates on one area of CAD: the design of computer systems. Within this area, it focusses on just two aspects of computer design, the specification and the simulation of digital systems. VLSI design requires support in many other CAD areas, induding automatic layout. IC fabrication analysis, test generation, and others. The problem of specification is unique, however, in that it i > often the first one encountered in large chip designs, and one that is unlikely ever to be completely automated. This is true because until a design's objectives are specified in a machine-readable form, there is no way for other CAD tools to verify that the target system meets them. And unless the specifications can be simulated, it is unlikely that designers will have confidence in them, since specifications are potentially erroneous themselves. (In this context the term target system refers to the hardware and/or software that will ultimately be fabricated. ) On the other hand, since the functionality of a VLSI chip is ultimately determined by its layout geometry, one might question the need for CAD tools that work with areas other than layout.

Batch chemical processing has in the past decade enjoyed a return to respectability as a valuable, effective, and often preferred mode of process operation. This book provides the first comprehensive and authoritative coverage that reviews the state of the art development in the field of batch chemical systems engineering, applications in various chemical industries, current practice in different parts of the world, and future technical challenges. Developments in enabling computing technologies such as simulation, mathematical programming, knowledge based systems, and prognosis of how these developments would impact future progress in the batch domain are covered. Design issues for complex unit processes and batch plants as well as operational issues such as control and scheduling are also addressed.

The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits under stringent time-to-market requirements is lagging behind integration capacity, so far keeping pace with still valid Moore s Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools, design methodologies and even a design paradigm shift, that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design more subtle, hierarchically loose, and handicraft-demanding has hindered a similar level of consensus and development.

Aiming at the core of the problem, Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the first two for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks.

Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits features a very detailed, tutorial, and in-depth coverage of all issues and must-have properties of reusable AMS blocks, as well as a thorough description of the methods and tools necessary to implement them. For the first time, this has been done hierarchically, covering one by one the different stages of the design flow, allowing us to examine how the reusable block yields its benefits, both in design time and correct performance."

This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.

Intelligent agents are one of the most promising business tools in our information rich world. An intelligent agent consists of a software system capable of performing intelligent tasks within a dynamic and unpredictable environment. They can be characterised by various attributes including: autonomous, adaptive, collaborative, communicative, mobile, and reactive. Many problems are not well defined and the information needed to make decisions is not available. These problems are not easy to solve using conventional computing approaches. Here, the intelligent agent paradigm may play a major role in helping to solve these problems. This book, written for application researchers, covers a broad selection of research results that demonstrate, in an authoritative and clear manner, the applications of agents within our information society.

Cellular Neural Networks (CNNs) constitute a class of nonlinear, recurrent and locally coupled arrays of identical dynamical cells that operate in parallel. ANALOG chips are being developed for use in applications where sophisticated signal processing at low power consumption is required. Signal processing via CNNs only becomes efficient if the network is implemented in analog hardware. In view of the physical limitations that analog implementations entail, robust operation of a CNN chip with respect to parameter variations has to be insured. By far not all mathematically possible CNN tasks can be carried out reliably on an analog chip; some of them are inherently too sensitive. This book defines a robustness measure to quantify the degree of robustness and proposes an exact and direct analytical design method for the synthesis of optimally robust network parameters. The method is based on a design centering technique which is generally applicable where linear constraints have to be satisfied in an optimum way. Processing speed is always crucial when discussing signal-processing devices. In the case of the CNN, it is shown that the setting time can be specified in closed analytical expressions, which permits, on the one hand, parameter optimization with respect to speed and, on the other hand, efficient numerical integration of CNNs. Interdependence between robustness and speed issues are also addressed. Another goal pursued is the unification of the theory of continuous-time and discrete-time systems. By means of a delta-operator approach, it is proven that the same network parameters can be used for both of these classes, even if their nonlinear output functions differ. More complex CNN optimization problems that cannot be solved analytically necessitate resorting to numerical methods. Among these, stochastic optimization techniques such as genetic algorithms prove their usefulness, for example in image classification problems. Since the inception of the CNN, the problem of finding the network parameters for a desired task has been regarded as a learning or training problem, and computationally expensive methods derived from standard neural networks have been applied. Furthermore, numerous useful parameter sets have been derived by intuition. In this book, a direct and exact analytical design method for the network parameters is presented. The approach yields solutions which are optimum with respect to robustness, an aspect which is crucial for successful implementation of the analog CNN hardware that has often been neglected. `This beautifully rounded work provides many interesting and useful results, for both CNN theorists and circuit designers.' Leon O. Chua

Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner workings of symbolic simulation. The core of this book focuses on new techniques that narrow the performance gap between the complexity of digital systems and the limited ability to verify them. In particular, it covers a range of solutions that exploit approximation and parametrization methods, including quasi-symbolic simulation, cycle-based symbolic simulation, and parameterizations based on disjoint-support decompositions.

In structuring this book, the author s hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research.

Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field.

Highlights:

• A discussion of the leading hardware verification techniques, including simulation and formal verification solutions
• Important concepts related to the underlying models and algorithms employed in the field
• The latest innovations in the area of symbolic simulation, exploiting techniques such as parametric forms and decomposition properties of Boolean functions
• Providing insights into possible new developments in the hardware verification

Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology.

Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all.

Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model.

Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog. It is a SystemVerilog version of the author's bestselling book Writing Testbenches: Functional Verification of HDL Models.

Constraint-Based Verification covers an emerging field in functional verification of electronic designs, referred to as the "constraint-based verification." The topics are developed in the context of a wide range of dynamic and static verification approaches including simulation, emulation, and formal methods. The goal is to show how constraints, or assertions, can be used towards automating the generation of testbenches, resulting in a seamless verification flow. Topics such as verification coverage, and connection with assertion based verification, are also covered.

The book targets verification engineers as well as researchers. It covers both methodological and technical issues. Particular stress is given to the latest advances in functional verification.

The research community has witnessed recent growth of interests in constraint-based functional verification. Various techniques have been developed. They are relatively new, but have reached a level of maturity so that they are appearing in commercial tools such as Vera and System Verilog.

This book details timing analysis and optimization techniques for circuits with level-sensitive memory elements. It contains a linear programming formulation applicable to the timing analysis of large scale circuits and includes a delay insertion methodology that improves the efficiency of clock skew scheduling. Coverage also provides a framework for and results from implementing timing optimization algorithms in a parallel computing environment.

On Optimal Interconnections for VLSI describes, from a geometric perspective, algorithms for high-performance, high-density interconnections during the global and detailed routing phases of circuit layout. First, the book addresses area minimization, with a focus on near-optimal approximation algorithms for minimum-cost Steiner routing. In addition to practical implementations of recent methods, the implications of recent results on spanning tree degree bounds and the method of Zelikovsky are discussed. Second, the book addresses delay minimization, starting with a discussion of accurate, yet algorithmically tractable, delay models. Recent minimum-delay constructions are highlighted, including provably good cost-radius tradeoffs, critical-sink routing algorithms, Elmore delay-optimal routing, graph Steiner arborescences, non-tree routing, and wiresizing. Third, the book addresses skew minimization for clock routing and prescribed-delay routing formulations. The discussion starts with early matching-based constructions and goes on to treat zero-skew routing with provably minimum wirelength, as well as planar clock routing. Finally, the book concludes with a discussion of multiple (competing) objectives, i.e., how to optimize area, delay, skew, and other objectives simultaneously. These techniques are useful when the routing instance has heterogeneous resources or is highly congested, as in FPGA routing, multi-chip packaging, and very dense layouts. Throughout the book, the emphasis is on practical algorithms and a complete self-contained development. On Optimal Interconnections for VLSI will be of use to both circuit designers (CAD tool users) as well as researchers and developers in the area of performance-driven physical design.

One of the foundations for change in our society comes from designing. Its genesis is the notion that the world around us either is unsuited to our needs or can be improved. The need for designing is driven by a society's view that it can improve or add value to human existence well beyond simple subsistence. As a consequence of designing the world which we inhabit is increasingly a designed rather than a naturally occurring one. In that sense it is an "artificial" world. Designing is a fundamental precursor to manufacturing, fabrication, construction or implementation. Design research aims to develop an understanding of designing and to produce models of designing that can be used to aid designing. Artificial intelligence has provided an environmental paradigm within which design research based on computational constructions, can be carried out. Design research can be carried out in variety of ways. It can be viewed as largely an empirical endeavour in which experiments are designed and executed in order to test some hypothesis about some design phenomenon or design behaviour. This is the approach adopted in cognitive science. It often manifests itself through the use of protocol studies of designers. The results of such research form the basis of a computational model. A second view is that design research can be carried out by positing axioms and then deriving consequences from them.

After a brief introduction to low-power VLSI design, the design space of ASIP instruction set architectures (ISAs) is introduced with a special focus on important features for digital signal processing. Based on the degrees of freedom offered by this design space, a consistent ASIP design flow is proposed: this design flow starts with a given application and uses incremental optimization of the ASIP hardware, of ASIP coprocessors and of the ASIP software by using a top-down approach and by applying application-specific modifications on all levels of design hierarchy. A broad range of real-world signal processing applications serves as vehicle to illustrate each design decision and provides a hands-on approach to ASIP design. Finally, two complete case studies demonstrate the feasibility and the efficiency of the proposed methodology and quantitatively evaluate the benefits of ASIPs in an industrial context.

Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density.

Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.

The Forum on Design Languages (FDL) is the European Forum to exchange experiences and learn new trends, in the application of languages and the associated design methods and tools, to design complex electronic systems. By offering several co-located workshops, this multi-faceted event gives an excellent opportunity to gain up-to-date knowledge across main aspects of such a wide field. All the workshops address as their common denominator the different application domains of system-design languages with the presentation of the latest research results and design experiences.
FDL'02 was organized as four focused workshops, Languages for Analog and Mixed-Signal system design, UML-based system specification and design, C/C++-based system design and Specification Formalisms for Proven design.

FDL served once more as the European Forum for electronic system design languages and consolidates as the main place in Europe where designers interested in design languages and their applications can meet and interchange experiences.

In this fourth book in the CHDL Series, a selection of the best papers presented in FDL'02 is published. System Specification and Design Languages contains outstanding research contributions in the four areas mentioned above. So, The Analog and Mixed-Signal system design contributions cover the new methodological approaches like AMS behavioral specification, mixed-signal modeling and simulation, AMS reuse and MEMs design using the new modeling languages such as VHDL-AMS, Verilog-AMS, Modelica and analog-mixed signal extensions to SystemC.

UML is the de-facto standard for SW development covering the early development stages of requirement analysis and system specification. The UML-based system specification and design contributions address latest results on hot-topic areas such as system profiling, performance analysis and UML application to complex, HW/SW embedded systems and SoC design.C/C++-for HW/SW systems design is entering standard industrial design flows. Selected papers cover system modeling, system verification and SW generation.

The papers from the Specification Formalisms for Proven design workshop present formal methods for system modeling and design, semantic integrity and formal languages such as ALPHA, HANDLE and B.

The Integrated Circuit (IC) industry has gone without a standardized verification approach for decades. This book defines a uniform, standardizable methodology for verifying the logical behavior of an integrated circuit, whether an I/O controller, a microprocessor, or a complete digital system. This book will help Engineers and managers responsible for IC development to bring a single, standards-based methodology to their R & D efforts, cutting costs and improving results.

Combinatorial optimisation is a ubiquitous discipline whose usefulness spans vast applications domains. The intrinsic complexity of most combinatorial optimisation problems makes classical methods unaffordable in many cases. To acquire practical solutions to these problems requires the use of metaheuristic approaches that trade completeness for pragmatic effectiveness. Such approaches are able to provide optimal or quasi-optimal solutions to a plethora of difficult combinatorial optimisation problems.

The application of metaheuristics to combinatorial optimisation is an active field in which new theoretical developments, new algorithmic models, and new application areas are continuously emerging. This volume presents recent advances in the area of metaheuristic combinatorial optimisation, with a special focus on evolutionary computation methods. Moreover, it addresses local search methods and hybrid approaches. In this sense, the book includes cutting-edge theoretical, methodological, algorithmic and applied developments in the field, from respected experts and with a sound perspective.

Along the years, rough set theory has earned a well-deserved reputation as a sound methodology for dealing with imperfect knowledge in a simple though mathematically sound way. This edited volume aims at continue stressing the benefits of applying rough sets in many real-life situations while still keeping an eye on topological aspects of the theory as well as strengthening its linkage with other soft computing paradigms. The volume comprises 11 chapters and is organized into three parts. Part 1 deals with theoretical contributions while Parts 2 and 3 focus on several real world data mining applications. Chapters authored by pioneers were selected on the basis of fundamental ideas/concepts rather than the thoroughness of techniques deployed. Academics, scientists as well as engineers working in the rough set, computational intelligence, soft computing and data mining research area will find the comprehensive coverage of this book invaluable.

In recent years, the issue of linkage in GEAs has garnered greater attention and recognition from researchers. Conventional approaches that rely much on ad hoc tweaking of parameters to control the search by balancing the level of exploitation and exploration are grossly inadequate. As shown in the work reported here, such parameters tweaking based approaches have their limits; they can be easily fooled by cases of triviality or peculiarity of the class of problems that the algorithms are designed to handle. Furthermore, these approaches are usually blind to the interactions between the decision variables, thereby disrupting the partial solutions that are being built up along the way.

Condition modelling and control is a technique used to enable decision-making in manufacturing processes of interest to researchers and practising engineering. Condition Monitoring and Control for Intelligent Manufacturing will be bought by researchers and graduate students in manufacturing and control and engineering, as well as practising engineers in industries such as automotive and packaging manufacturing.

Evolutionary algorithms are sophisticated search methods that have been found to be very efficient and effective in solving complex real-world multi-objective problems where conventional optimization tools fail to work well. Despite the tremendous amount of work done in the development of these algorithms in the past decade, many researchers assume that the optimization problems are deterministic and uncertainties are rarely examined. The primary motivation of this book is to provide a comprehensive introduction on the design and application of evolutionary algorithms for multi-objective optimization in the presence of uncertainties. In this book, we hope to expose the readers to a range of optimization issues and concepts, and to encourage a greater degree of appreciation of evolutionary computation techniques and the exploration of new ideas that can better handle uncertainties. "Evolutionary Multi-Objective Optimization in Uncertain Environments: Issues and Algorithms" is intended for a wide readership and will be a valuable reference for engineers, researchers, senior undergraduates and graduate students who are interested in the areas of evolutionary multi-objective optimization and uncertainties.

The design of computer systems to be embedded in critical real-time applications is a complex task. Such systems must not only guarantee to meet hard real-time deadlines imposed by their physical environment, they must guarantee to do so dependably, despite both physical faults (in hardware) and design faults (in hardware or software). A fault-tolerance approach is mandatory for these guarantees to be commensurate with the safety and reliability requirements of many life- and mission-critical applications. This book explains the motivations and the results of a collaborative project', whose objective was to significantly decrease the lifecycle costs of such fault tolerant systems. The end-user companies participating in this project already deploy fault-tolerant systems in critical railway, space and nuclear-propulsion applications. However, these are proprietary systems whose architectures have been tailored to meet domain-specific requirements. This has led to very costly, inflexible, and often hardware-intensive solutions that, by the time they are developed, validated and certified for use in the field, can already be out-of-date in terms of their underlying hardware and software technology."