The chapters of this book summarize the lectures delivered du ring the NATO Advanced Study Institute (ASI) on Computational Methods in Mechanisms, that took place in the Sts. Constantin and Elena Resort, near Varna, on the Bulgarian Coast of the Black Sea, June 16-28, 1997. The purpose of the ASI was to bring together leading researchers in the area of mechanical systems at large, with special emphasis in the computational issues around their analysis, synthesis, and optimization, during two weeks of lectures and discussion. A total of 89 participants from 23 count ries played an active role during the lectures and sessions of contributed papers. Many of the latter are being currently reviewed for publication in specialized journals. The subject of the book is mechanical systems, Le., systems composed of rigid and flexible bodies, coupled by mechanical means so as to constrain their various bodies in a goal-oriented manner, usually driven under computer con trol. Applications of the discipline are thus of the most varied nature, ranging from transportation systems to biomedical devices. U nder normal operation conditions, the constitutive bodies of a mechanical system can be consid ered to be rigid, the rigidity property then easing dramatically the analysis of the kinematics and dynamics of the system at hand. Examples of these systems are the suspension of a terrestrial vehicle negotiating a curve at speeds within the allowed or recommended limits and the links of multiaxis industrial robots performing conventional pick-and-place operations."

Hardware veri?cation is the process of checking whether a design conforms to its speci?cations of functionality and timing. In today's design processes it becomes more and more important. Very large scale integrated (VLSI) circuits and the resulting digital systems have conquered a place in almost all areas of our life, even in security sensitive applications. Complex digital systems control airplanes, have been used in banks and on intensive-care units. Hence, the demand for error-free designs is more important than ever. In addition, economic reasons underline this demand as well. The design and production process of present day VLSI-circuits is highly time- and cost-intensive. Mo- over, it is nearly impossible to repair integrated circuits. Thus, it is desirable to detect design errors early in the design process and not just after producing the prototype chip. All these facts are re?ected by developing and prod- tion statistics of present day companies. For example, In?neon Technologies [118] assumed that about 60% to 80% of the overall design time was spent for veri?cation in 2000. Other sources cite the 3-to-1 head count ratio between veri?cation engineers and logic designers. This shows that verifying logical correctness of the design of hardware systems is a major gate to the problem of time-to-market (cf. [113]). With the chip complexity constantly increasing, the dif?culty as well as the - portance of functional veri?cation of new product designs has been increased. It is not only more important to get error-free designs.

Formal verification has become one of the most important steps in circuit design. Since circuits can contain several million transistors, verification of such large designs becomes more and more difficult. Pure simulation cannot guarantee the correct behavior and exhaustive simulation is often impossible. However, many designs, like ALUs, have very regular structures that can be easily described at a higher level of abstraction. For example, describing (and verifying) an integer multiplier at the bit-level is very difficult, while the verification becomes easy when the outputs are grouped to build a bit-string. Recently, several approaches for formal circuit verification have been proposed that make use of these regularities. These approaches are based on Word-Level Decision Diagrams (WLDDs) which are graph-based representations of functions (similar to BDDs) that allow for the representation of functions with a Boolean range and an integer domain. Formal Verification of Circuits is devoted to the discussion of recent developments in the field of decision diagram-based formal verification. Firstly, different types of decision diagrams (including WLDDs) are introduced and theoretical properties are discussed that give further insight into the data structure. Secondly, implementation and minimization concepts are presented. Applications to arithmetic circuit verification and verification of designs specified by hardware description languages are described to show how WLDDs work in practice. Formal Verification of Circuits is intended for CAD developers and researchers as well as designers using modern verification tools. It will help people working with formal verification (in industry or academia) to keep informed about recent developments in this area.

This book provides a complete overview of the field of carbon nanotube electronics. It covers materials and physical properties, synthesis and fabrication processes, devices and circuits, modeling, and finally novel applications of nanotube-based electronics. The book introduces fundamental device physics and circuit concepts of 1-D electronics. At the same time it provides specific examples of the state-of-the-art nanotube devices.

The papers collected in this volume were originally presented at the conference on Design and Decision Support Systems in Architecture and Urban Planning that was held in Mierlo, the Netherlands in July 1992. This conference was organized as one of the events celebrating the 25th anniversary of the founding of the Faculty of Architecture, Building and Planning at Eindhoven University of Technology. The organizing committee had a strong feeling that many interesting developments in this area were emerging within different institutional frameworks and informal networks that do not interact frequently. For example, scholars working on architectural problems are not particularly familiar with computer applications in urban planning. Likewise, although many computer-aided design systems claim to be based on principles of design methodology, serious discussions on the methodological underpinnings of such systems are relatively scarce. Consequently, we may have little opportunity to learn how scholars in closely related disciplines approach specific design or planning problems.

The world of wireless communications is changing very rapidly since a few years. The introduction of digital data communication in combination with digital signal process ing has created the foundation for the development of many new wireless applications. High-quality digital wireless networks for voice communication with global and local coverage, like the GSM and DECT system, are only faint and early examples of the wide variety of wireless applications that will become available in the remainder of this decade. The new evolutions in wireless communications set new requirements for the trans ceivers (transmitter-receivers). Higher operating frequencies, a lower power consump tion and a very high degree of integration, are new specifications which ask for design approaches quite different from the classical RF design techniques. The integrata bility and power consumption reduction of the digital part will further improve with the continued downscaling of technologies. This is however completely different for the analog transceiver front-end, the part which performs the interfacing between the antenna and the digital signal processing. The analog front-end's integratability and power consumption are closely related to the physical limitations of the transceiver topology and not so much to the scaling of the used technology. Chapter 2 gives a detailed study of the level of integration in current transceiver realization and analyzes their limitations. In chapter 3 of this book the complex signal technique for the analysis and synthesis of multi-path receiver and transmitter topologies is introduced."

In the early days of VLSI, the design of the power distribution for an integrated cir cuit was rather simple. Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler. Few available wiring layers forced floorplans that allowed simple, planar (non-over lapping) power networks. Lower speeds and circuit density made the choice of the wire widths easier: we made them just fat enough to avoid resistive voltage drops due to switching currents in the supply network. And we just didn't need enormous num bers of power and ground pins on the package for the chips to work. It's not so simple any more. Increased integration has forced us to focus on reliability concerns such as metal elec tromigration, which affects wire sizing decisions in the power network. Extra metal layers have allowed more flexibility in the topological layout of the power networks."

By virtue of their special algebraic structures, Pythagorean-hodograph (PH) curves offer unique advantages for computer-aided design and manufacturing, robotics, motion control, path planning, computer graphics, animation, and related fields. This book offers a comprehensive and self-contained treatment of the mathematical theory of PH curves, including algorithms for their construction and examples of their practical applications. It emphasizes the interplay of ideas from algebra and geometry and their historical origins and includes many figures, worked examples, and detailed algorithm descriptions.

Today, Fuzzy Set Theory is the core discipline of so-called soft computing, and provides new impetus for research in the field of artificial intelligence. In this fascinating book, the history of Fuzzy Set Theory and the ways it was first used are incorporated into the history of 20th century science and technology. Influences from philosophy, system theory and cybernetics stemming from the earliest part of the 20th century are considered alongside those of communication and control theory from mid-century.

Integrated System-Level Modeling of Network-on-Chip Enabled Multi-Processor Platforms first gives a comprehensive update on recent developments in the area of SoC platforms and ESL design methodologies. The main contribution is the rigorous definition of a framework for modeling at the timing approximate level of abstraction. Subsequently this book presents a set of tools for the creation and exploration of timing approximate SoC platform models.

Here is a textbook for senior undergraduate and graduate level students that offers a novel and systematic look into the dynamics of MEMS. It includes numerous solved examples together with the proposed problems. The material to be found here will also be of interest to researchers with a non-mechanical background. The book focuses on the mechanical domain, specifically the dynamic sub-domain, and provides an in-depth treatment of problems that involve reliable modeling, analysis and design.

At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture.

In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability.

Design for Manufacturability and Statistical Design: A Comprehensive Approach presents a comprehensive overview of methods that need to be mastered in understanding state-of-the-art design for manufacturability and statistical design methodologies. Broadly, design for manufacturability is a set of techniques that attempt to fix the systematic sources of variability, such as those due to photolithography and CMP. Statistical design, on the other hand, deals with the random sources of variability. Both paradigms operate within a common framework, and their joint comprehensive treatment is one of the objectives of this book and an important differentation.

The material in this book was presented in the tutorial programme of the Eurographics '87 Conference, held in Amsterdam, The Netherlands, 1987. The book contains eight contributions, from leading experts in each field. Major aspects of computer graphics fundamentals, interactive techniques and three-dimensional modelling techniques are discussed and a state-of-the-art survey on the increasingly important area of desktop publishing is given. The theory of fractals is covered by presenting a thorough treatment of their mathematics and programming. Furthermore, overviews of several topics, such as the theory and methods of modelling three-dimensional shapes and objects, the fundamental concepts and current advances in user interface management systems, and existing CAD-interface specifications, are included. The book will be of interest to systems designers, application programmers and researchers who wish to gain a deeper knowledge of the state-of-the-art in the areas covered.

In this book, the author has presented an introduction to the practical application of some of the essential technical topics related to computer-aided engineering (CAE). These topics include interactive computer graphics (ICG), computer-aided design (CAD), computer and computer-integrated manufacturing (CIM). aided analysis (CAA) Unlike the few texts available, the present work attempts to bring all these seemingly specialised topics together and to demonstrate their integration in the design process through practical applications to real engineering problems and case studies. This book is the result of the author's research and teaching activities for several years of postgraduate and undergraduate courses in mechanical design of rotating machinery, computer-aided engineering, of finite elements, solid mechanics, engineering practical applications and properties of materials at Cranfield Institute of dynamics Technology, Oxford Engineering Science and the University of Manchester Institute of Science and Technology (UMIST). It was soon realised that no books on the most powerful and versatile tools available to engineering designers existed. To satisfy this developing need, this book, on the use of computers to aid the design process and to integrate design, analysis and manufacture, was prepared."

In recent years meshless/meshfree methods have gained considerable attention in engineering and applied mathematics. The variety of problems that are now being addressed by these techniques continues to expand and the quality of the results obtained demonstrates the effectiveness of many of the methods currently available. The book presents a significant sample of the state of the art in the field with methods that have reached a certain level of maturity while also addressing many open issues. The book collects extended original contributions presented at the Second ECCOMAS Conference on Meshless Methods held in 2007 in Porto. The list of contributors reveals a fortunate mix of highly distinguished authors as well as quite young but very active and promising researchers, thus giving the reader an interesting and updated view of different meshless approximation methods and their range of applications. The material presented is appropriate for researchers, engineers, physicists, applied mathematicians and graduate students interested in this active research area.

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

AND BACKGROUND 1. 1 CAD, Specification and Simulation Computer Aided Design (CAD) is today a widely used expression referring to the study of ways in which computers can be used to expedite the design process. This can include the design of physical systems, architectural environments, manufacturing processes, and many other areas. This book concentrates on one area of CAD: the design of computer systems. Within this area, it focusses on just two aspects of computer design, the specification and the simulation of digital systems. VLSI design requires support in many other CAD areas, induding automatic layout. IC fabrication analysis, test generation, and others. The problem of specification is unique, however, in that it i > often the first one encountered in large chip designs, and one that is unlikely ever to be completely automated. This is true because until a design's objectives are specified in a machine-readable form, there is no way for other CAD tools to verify that the target system meets them. And unless the specifications can be simulated, it is unlikely that designers will have confidence in them, since specifications are potentially erroneous themselves. (In this context the term target system refers to the hardware and/or software that will ultimately be fabricated. ) On the other hand, since the functionality of a VLSI chip is ultimately determined by its layout geometry, one might question the need for CAD tools that work with areas other than layout.

Batch chemical processing has in the past decade enjoyed a return to respectability as a valuable, effective, and often preferred mode of process operation. This book provides the first comprehensive and authoritative coverage that reviews the state of the art development in the field of batch chemical systems engineering, applications in various chemical industries, current practice in different parts of the world, and future technical challenges. Developments in enabling computing technologies such as simulation, mathematical programming, knowledge based systems, and prognosis of how these developments would impact future progress in the batch domain are covered. Design issues for complex unit processes and batch plants as well as operational issues such as control and scheduling are also addressed.

The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits under stringent time-to-market requirements is lagging behind integration capacity, so far keeping pace with still valid Moore s Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools, design methodologies and even a design paradigm shift, that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design more subtle, hierarchically loose, and handicraft-demanding has hindered a similar level of consensus and development.

Aiming at the core of the problem, Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the first two for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, and guidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks.

Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits features a very detailed, tutorial, and in-depth coverage of all issues and must-have properties of reusable AMS blocks, as well as a thorough description of the methods and tools necessary to implement them. For the first time, this has been done hierarchically, covering one by one the different stages of the design flow, allowing us to examine how the reusable block yields its benefits, both in design time and correct performance."

This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.

Intelligent agents are one of the most promising business tools in our information rich world. An intelligent agent consists of a software system capable of performing intelligent tasks within a dynamic and unpredictable environment. They can be characterised by various attributes including: autonomous, adaptive, collaborative, communicative, mobile, and reactive. Many problems are not well defined and the information needed to make decisions is not available. These problems are not easy to solve using conventional computing approaches. Here, the intelligent agent paradigm may play a major role in helping to solve these problems. This book, written for application researchers, covers a broad selection of research results that demonstrate, in an authoritative and clear manner, the applications of agents within our information society.

Cellular Neural Networks (CNNs) constitute a class of nonlinear, recurrent and locally coupled arrays of identical dynamical cells that operate in parallel. ANALOG chips are being developed for use in applications where sophisticated signal processing at low power consumption is required. Signal processing via CNNs only becomes efficient if the network is implemented in analog hardware. In view of the physical limitations that analog implementations entail, robust operation of a CNN chip with respect to parameter variations has to be insured. By far not all mathematically possible CNN tasks can be carried out reliably on an analog chip; some of them are inherently too sensitive. This book defines a robustness measure to quantify the degree of robustness and proposes an exact and direct analytical design method for the synthesis of optimally robust network parameters. The method is based on a design centering technique which is generally applicable where linear constraints have to be satisfied in an optimum way. Processing speed is always crucial when discussing signal-processing devices. In the case of the CNN, it is shown that the setting time can be specified in closed analytical expressions, which permits, on the one hand, parameter optimization with respect to speed and, on the other hand, efficient numerical integration of CNNs. Interdependence between robustness and speed issues are also addressed. Another goal pursued is the unification of the theory of continuous-time and discrete-time systems. By means of a delta-operator approach, it is proven that the same network parameters can be used for both of these classes, even if their nonlinear output functions differ. More complex CNN optimization problems that cannot be solved analytically necessitate resorting to numerical methods. Among these, stochastic optimization techniques such as genetic algorithms prove their usefulness, for example in image classification problems. Since the inception of the CNN, the problem of finding the network parameters for a desired task has been regarded as a learning or training problem, and computationally expensive methods derived from standard neural networks have been applied. Furthermore, numerous useful parameter sets have been derived by intuition. In this book, a direct and exact analytical design method for the network parameters is presented. The approach yields solutions which are optimum with respect to robustness, an aspect which is crucial for successful implementation of the analog CNN hardware that has often been neglected. `This beautifully rounded work provides many interesting and useful results, for both CNN theorists and circuit designers.' Leon O. Chua

Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner workings of symbolic simulation. The core of this book focuses on new techniques that narrow the performance gap between the complexity of digital systems and the limited ability to verify them. In particular, it covers a range of solutions that exploit approximation and parametrization methods, including quasi-symbolic simulation, cycle-based symbolic simulation, and parameterizations based on disjoint-support decompositions.

In structuring this book, the author s hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research.

Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field.

Highlights:

• A discussion of the leading hardware verification techniques, including simulation and formal verification solutions
• Important concepts related to the underlying models and algorithms employed in the field
• The latest innovations in the area of symbolic simulation, exploiting techniques such as parametric forms and decomposition properties of Boolean functions
• Providing insights into possible new developments in the hardware verification