System designers, computer scientists and engineers have c- tinuously invented and employed notations for modeling, speci- ing, simulating, documenting, communicating, teaching, verifying and controlling the designs of digital systems. Initially these s- tems were represented via electronic and fabrication details. F- lowing C. E. Shannon's revelation of 1948, logic diagrams and Boolean equations were used to represent digital systems in a fa- ion that de-emphasized electronic and fabrication detail while revealing logical behavior. A small number of circuits were made available to remove the abstraction of these representations when it was desirable to do so. As system complexity grew, block diagrams, timing charts, sequence charts, and other graphic and symbolic notations were found to be useful in summarizing the gross features of a system and describing how it operated. In addition, it always seemed necessary or appropriate to augment these documents with lengthy verbal descriptions in a natural language. While each notation was, and still is, a perfectly valid means of expressing a design, lack of standardization, conciseness, and f- mal definitions interfered with communication and the understa- ing between groups of people using different notations. This problem was recognized early and formal languages began to evolve in the 1950s when I. S. Reed discovered that flip-flop input equations were equivalent to a register transfer equation, and that xvi tor-like notation. Expanding these concepts Reed developed a no- tion that became known as a Register Transfer Language (RTL).

Communication protocols are rules whereby meaningful communication can be exchanged between different communicating entities. In general, they are complex and difficult to design and implement. Specifications of communication protocols written in a natural language (e.g. English) can be unclear or ambiguous, and may be subject to different interpretations. As a result, independent implementations of the same protocol may be incompatible. In addition, the complexity of protocols make them very hard to analyze in an informal way. There is, therefore, a need for precise and unambiguous specification using some formal languages. Many protocol implementations used in the field have almost suffered from failures, such as deadlocks. When the conditions in which the protocols work correctly have been changed, there has been no general method available for determining how they will work under the new conditions. It is necessary for protocol designers to have techniques and tools to detect errors in the early phase of design, because the later in the process that a fault is discovered, the greater the cost of rectifying it. Protocol verification is a process of checking whether the interactions of protocol entities, according to the protocol specification, do indeed satisfy certain properties or conditions which may be either general (e.g., absence of deadlock) or specific to the particular protocol system directly derived from the specification. In the 80s, an ISO (International Organization for Standardization) working group began a programme of work to develop formal languages which were suitable for Open Systems Interconnection (OSI). This group called such languages Formal Description Techniques (FDTs). Some of the objectives of ISO in developing FDTs were: enabling unambiguous, clear and precise descriptions of OSI protocol standards to be written, and allowing such specifications to be verified for correctness. There are two FDTs standardized by ISO: LOTOS and Estelle. Communication Protocol Specification and Verification is written to address the two issues discussed above: the needs to specify a protocol using an FDT and to verify its correctness in order to uncover specification errors in the early stage of a protocol development process. The readership primarily consists of advanced undergraduate students, postgraduate students, communication software developers, telecommunication engineers, EDP managers, researchers and software engineers. It is intended as an advanced undergraduate or postgraduate textbook, and a reference for communication protocol professionals.

The arrival and popularity of multi-core processors has sparked a renewed interest in the development of parallel programs. Similarly, the availability of low-cost microprocessors and sensors has generated a great interest in embedded real-time programs. This book provides students and programmers whose backgrounds are in traditional sequential programming with the opportunity to expand their capabilities into parallel, embedded, real-time and distributed computing. It also addresses the theoretical foundation of real-time scheduling analysis, focusing on theory that is useful for actual applications. Written by award-winning educators at a level suitable for undergraduates and beginning graduate students, this book is the first truly entry-level textbook in the subject. Complete examples allow readers to understand the context in which a new concept is used, and enable them to build and run the examples, make changes, and observe the results.

Analog Behavioral Modeling With The Verilog-A Language provides the IC designer with an introduction to the methodologies and uses of analog behavioral modeling with the Verilog-A language. In doing so, an overview of Verilog-A language constructs as well as applications using the language are presented. In addition, the book is accompanied by the Verilog-A Explorer IDE (Integrated Development Environment), a limited capability Verilog-A enhanced SPICE simulator for further learning and experimentation with the Verilog-A language. This book assumes a basic level of understanding of the usage of SPICE-based analog simulation and the Verilog HDL language, although any programming language background and a little determination should suffice. From the Foreword: `Verilog-A is a new hardware design language (HDL) for analog circuit and systems design. Since the mid-eighties, Verilog HDL has been used extensively in the design and verification of digital systems. However, there have been no analogous high-level languages available for analog and mixed-signal circuits and systems. Verilog-A provides a new dimension of design and simulation capability for analog electronic systems. Previously, analog simulation has been based upon the SPICE circuit simulator or some derivative of it. Digital simulation is primarily performed with a hardware description language such as Verilog, which is popular since it is easy to learn and use. Making Verilog more worthwhile is the fact that several tools exist in the industry that complement and extend Verilog's capabilities ... Behavioral Modeling With the Verilog-A Language provides a good introduction and starting place for students and practicing engineers with interest in understanding this new level of simulation technology. This book contains numerous examples that enhance the text material and provide a helpful learning tool for the reader. The text and the simulation program included can be used for individual study or in a classroom environment ...' Dr. Thomas A. DeMassa, Professor of Engineering, Arizona State University

NATO's Division of Scientific and Environmental Affairs sponsored this Advan ced Study Institute because it was felt to be timely to cover this important and challengjng subject for the first time in the framework of NATO's ASI programme. The significance of real-time systems in everyones' life is rapidly growing. The vast spectrum of these systems can be characterised by just a few examples of increasing complexity: controllers in washing machines, air traffic control systems, control and safety systems of nuclear power plants and, finally, future military systems like the Strategic Defense Initiative (SDI). The import ance of such systems for the well-being of people requires considerable efforts in research and development of highly reliable real-time systems. Furthermore, the competitiveness and prosperity of entire nations now depend on the early app lication and efficient utilisation of computer integrated manufacturing systems (CIM), of which real-time systems are an essential and decisive part. Owing to its key significance in computerised defence systems, real-time computing has also a special importance for the Alliance. The early research and development activities in this field in the 1960s and 1970s aimed towards improving the then unsatisfactory software situation. Thus, the first high-level real-time languages were defined and developed: RTL/2, Coral 66, Procol, LTR, and PEARL. In close connection with these language develop ments and with the utilisation of special purpose process control peripherals, the research on real-time operating systems advanced considerably."

Oracle Exadata Recipes takes an example-based, problem/solution approach in showing how to size, install, configure, manage, monitor, optimize, and migrate Oracle database workloads on and to the Oracle Exadata Database Machine. Whether you're an Oracle Database administrator, Unix/Linux administrator, storage administrator, network administrator, or Oracle developer, Oracle Exadata Recipes provides effective and proven solutions to accomplish a wide variety of tasks on the Exadata Database Machine. You can feel confident using the reliable solutions that are demonstrated in this book in your enterprise Exadata environment. Managing Oracle Exadata is unlike managing a traditional Oracle database. Oracle's Exadata Database Machine is a pre-configured engineered system comprised of hardware and software, built to deliver extreme performance for Oracle Database workloads. Exadata delivers extreme performance by offering an optimally balanced hardware infrastructure with fast components at each layer of the engineered technology stack, as well as a unique set of Oracle software features designed to leverage the high-performing hardware infrastructure by reducing I/O demands.Let Oracle Exadata Recipes help you translate your existing Oracle Database knowledge into the exciting new growth area that is Oracle Exadata. * Helps extend your Oracle Database skillset to the fast-growing, Exadata platform * Presents information on managing Exadata in a helpful, example-based format * Clearly explains unique Exadata software and hardware features What you'll learn * Install and configure Exadata * Manage your Exadata hardware infrastructure * Monitor and troubleshoot performance issues * Manage smart scan and cell offload processing * Take advantage of Hybrid Columnar Compression * Deploy Smart Flash Cache and Smart Flash Logging * Ensure the health of your Exadata environment Who this book is for Oracle Exadata Recipes is for Oracle Database administrators, Unix/Linux administrators, storage administrators, backup administrators, network administrators, and Oracle developers who want to quickly learn to develop effective and proven solutions without reading through a lengthy manual scrubbing for techniques. Readers in a hurry will appreciate the recipe format that sets up solutions to common tasks as the centerpiece of the book.Table of Contents * Exadata Hardware * Exadata Software * How Oracle Works on Exadata * Workload Qualification * Sizing Exadata * Preparing for Exadata * Administration and Diagnostics Utilities * Backup and Recovery * Storage Administration * Network Administration * Patching and Upgrades * Security * Monitoring Exadata Storage Cells * Host and Database Performance Monitoring * Smart Scan and Cell Offload * Hybrid Columnar Compression * I/O Resource Management and Instance Caging * Smart Flash Cache and Smart Flash Logging * Storage Indexes * Post-Installation Monitoring Tasks * Post-Install Database Tasks

A Guide to VHDL is intended for the working engineer who needs to develop, document, simulate and synthesize a design using the VHDL language. It is for system and chip designers who are working with VHDL CAD tools, and who have some experience programming in Fortran, Pascal, or C and have used a logic simulator. A Guide to VHDL includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises invluded in the chapters can be run to reinforce the learning experience. For practical purposes, this book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. A Guide to VHDL can be used as a primer, since its contents are appropriate for an introductory course in VHDL.

Physicians, lawyers, engineers, architects, financial analysts, and other pro fessionals articulate an increasing need for support by intelligent workstations for decision making, analysis, communication, and other activities. "Intelligent Workstations for Professionals" is the collection of papers presented by inter national scientists at a symposium and workshop in March 1992. Requirements from potential users, studies of their behavior as well as approaches and aspects oftechnical realizations of "intelligent" functions are introduced. Eight contributions from members of the Center for Information and Tele communication Technology (Clrn of Northwestern University, Wisconsin Whitewater University, and the Children's Memorial Hospital deal with the latest findings of the UNIS (Users' Needs for Intelligent Systems) project, which is designed to identify needs and wishes from professionals for intelligent sup port systems and the potential barriers to adoption and use of such systems. The remaining papers concentrate on new approaches and techniques that en hance the "intelligence" of future workstations. They tackle issues like architectural trends in workstation design, the combination of workstations with HDTV and speech processing, automatic reading and understanding of documents, the automated development of software, or the processing of in exact knowledge. These papers were contributed by members of the DFKI GmbH (German Research Institute for Artificial Intelligence), GMD mbH (German Society for Mathematics and Data Processing), Siemens Gammasonics Inc., Siemens Nixdorf Informationssysteme AG and Siemens AG."

th This volume gathers together the technical papers presented at the 8 European Conference on Computer Supported Cooperative Work (ECSCW), held in Helsinki Finland. ECSCW is an international forum for multidisciplinary research covering the technical, empirical, and theoretical aspects of collaboration and computer systems. The 20 papers presented here have been selected via a rigorous reviewing process from 110 submissions. Both the number of submissions and the quality of the selected papers are testimony to the diversity and energy of the CSCW community. We trust that you will find the papers interesting and that they will serve to stimulate further quality work within the community. The technical papers are complemented by a wider set of activities at ECSCW 2003, including tutorials, workshops, demonstrations, videos, posters and a doctoral colloquium. Together these provide rich opportunities for discussion, learning and exploration of the more recent and novel issues in the field. This conference could not have taken place without considerable enthusiasm, support and participation, not to mention the hard work of a number of people. In particular, we would like to thank the following: * The authors, representing over 17 countries and 97 institutions, who submitted a paper. So many submissions of such high quality are the basis of a good conference. * The members of the program committee who so diligently reviewed and discussed papers. Their collective decisions result in a good scientific program and their feedback to authors strengthens the work of the community.

Speech technology - the use of speech as a means of sending information to, and receiving information from computer systems has been in use as a research tool for many years. Only recently has it begun to move out of the laboratory and into commercially worthwhile applications, first with compressed and synthesised spoken messages, then with computer recognition of spoken messages, and today with diverse applications involving both recognition and reproduction of human speech. We have written this book because we believe the technology has now advanced to the point where many more applications of voice recognition and response are both feasible and economically attractive. Computers that can understand everyday speech are still a distant prospect, but provided the limitations of present day equipment are clearly understood there is much that can be achieved with it. Our aim is to show, in non-technical language, what is now possible with the help of speech technology. The text includes many examples of current applications in industry, commerce and other fields, and we have selected five current industrial applications combining speech recognition and response for more detailed attention. Industrial cases have been chosen both because we see industry as an important growth area for speech applications in the next few years, and because it presents some of the greatest difficulties in speech recognition - if you can make it work in industry, then you can make it work almost anywhere."

Based on the highly successful second edition, this extended edition of "SystemVerilog for Verification: A Guide to Learning the Testbench Language Features" teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill.

In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students' understanding of the material. Other features of this revision include: New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standardDescriptions of UVM features such as factories, the test registry, and the configuration databaseExpanded code samples and explanations Numerous samples that have been tested on the major SystemVerilog simulators

"SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition "is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.
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Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplishment, have you ever had someone ask you, "Are you good or are you just lucky?"? Many design projects depend on blind luck in hopes that the chip will work. Other's, just adamantly rely on their own abilities to bring the chip to success. ill either case, how can we tell the difference between being good or lucky? There must be a better way not to fail. Failure. No one likes to fail. ill his book, "The Logic of Failure", Dietrich Domer argues that failure does not just happen. A series of wayward steps leads to disaster. Often these wayward steps are not really logical, decisive steps, but more like default omissions. Anti-planning if you will, an ad-hoc approach to doing something. To not plan then, is to fail.

The Verilog language is a hardware description language which provides a means of specifying a digital system at a wide range of levels of abstraction. The language supports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of a description. Verilog was originally designed in the winter of 1983/84 as a proprietary verification/simulation product. Since then, several other proprietary analysis tools have been developed around the language, including a fault simulator and a timing analyzer; the language being instrumental in providing consistency across these tools. Now, the language is openly available for any tool to read and write. This book introduces the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Where possible, we have stayed away from simulator-specific details and concentrated on design specification, but have included enough information to be able to have working executable models. The book takes a tutorial approach to presenting the language.

VHDL and FPLDs in Digital Systems Design, Prototyping and Customization treats three aspects of digital systems: design, prototyping and customization, in an integrated manner using two technologies. The two technologies are VHSIC Hardware Description Language (VHDL) and Field-Programmable Logic Devices (FPLDs). VHDL is used for modeling and specification; FPLDs are used for implementation. VHDL and FPLDs in Digital Systems Design, Prototyping and Customization is divided into three parts. Part I provides an introduction to the basic features of VHDL with emphasis on modeling and design. All types of VHDL models including behavioral, structural and dataflow models are presented. Part 2 is a bridge to designing and prototyping using FPLDs as the prototyping and implementation technology. Part 3 contains a number of examples and case studies that demonstrate the effectiveness of using VHDL and FPLDs in the design of real systems. VHDL and FPLDs in Digital Systems Design, Prototyping and Customization is an invaluable comprehensive reference for the digital designer. This work includes examples and software tied to real-world FPLDs.The reader can see how the material presented applies to real-world devices and can experiment with the software. Also included are large-scale designs like the FLIX microcomputer that demonstrates the power of VHDL.

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Hardware description languages (HDL) such as VHDL and Verilog have found their way into almost every aspect of the design of digital hardware systems. Since their inception they gradually proved to be an essential part of modern design methodologies and design automation tools, ever exceeding their original goals of being description and simulation languages. Their use for automatic synthesis, formal proof, and testing are good examples. So far, HDLs have been mainly dealing with digital systems. However, integrated systems designed today require more and more analog parts such as A/D and D/A converters, phase locked loops, current mirrors, etc. The verification of the complete system therefore asks for the use of a single language. Using VHDL or Verilog to handle analog descriptions is possible, as it is shown in this book, but the real power is coming from true mixed-signal HDLs that integrate discrete and continuous semantics into a unified framework. Analog HDLs (AHDL) are considered here a subset of mixed-signal HDLs as they intend to provide the same level of features as HDLs do but with a scope limited to analog systems, possibly with limited support of discrete semantics. Analog and Mixed-Signal Hardware Description Languages covers several aspects related to analog and mixed-signal hardware description languages including: The use of a digital HDL for the description and the simulation of analog systems The emergence of extensions of existing standard HDLs that provide true analog and mixed-signal HDLs. The use of analog and mixed-signal HDLs for the development of behavioral models of analog (electronic) building blocks (operational amplifier, PLL) and for the design of microsystems that do not only involve electronic parts. The use of a front-end tool that eases the description task with the help of a graphical paradigm, yet generating AHDL descriptions automatically. Analog and Mixed-Signal Hardware Description Languages is the first book to show how to use these new hardware description languages in the design of electronic components and systems. It is necessary reading for researchers and designers working in electronic design.

Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs.

The great advances made in large-scale integration of semiconductors and the resulting cost-effective digital processors and data storage devices determine the present development of automation. The application of digital techniques to process automation started in about 1960, when the first process computer was installed. From about 1970 process computers with cathodic ray tube display have become standard equipment for larger automation systems. Until about 1980 the annual increase of process computers was about 20 to 30%. The cost of hardware has already then shown a tendency to decrease, whereas the relative cost of user software has tended to increase. Because of the high total cost the first phase of digital process automation is characterized by the centralization of many functions in a single (though sometimes in several) process computer. Application was mainly restricted to medium and large processes. Because of the far-reaching consequences of a breakdown in the central computer parallel standby computers or parallel back-up systems had to be provided. This meant a substantial increase in cost. The tendency to overload the capacity and software problems caused further difficulties. In 1971 the first microprocessors were marketed which, together with large-scale integrated semiconductor memory units and input/output modules, can be assem bled into cost-effective microcomputers. These microcomputers differ from process computers in fewer but higher integrated modules and in the adaptability of their hardware and software to specialized, less comprehensive tasks."

Standardization of hardware description languages and the availability of synthesis tools has brought about a remarkable increase in the productivity of hardware designers. Yet design verification methods and tools lag behind and have difficulty in dealing with the increasing design complexity. This may get worse because more complex systems are now constructed by (re)using Intellectual Property blocks developed by third parties. To verify such designs, abstract models of the blocks and the system must be developed, with separate concerns, such as interface communication, functionality, and timing, that can be verified in an almost independent fashion. Standard Hardware Description Languages such as VHDL and Verilog are inspired by procedural `imperative' programming languages in which function and timing are inherently intertwined in the statements of the language. Furthermore, they are not conceived to state the intent of the design in a simple declarative way that contains provisions for design choices, for stating assumptions on the environment, and for indicating uncertainty in system timing. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method presents a description methodology that was inspired by Timing Diagrams and Process Algebras, the so-called Hierarchical Annotated Diagrams. It is suitable for specifying systems with complex interface behaviors that govern the global system behavior. A HADD specification can be converted into a behavioral real-time model in VHDL and used to verify the surrounding logic, such as interface transducers. Also, function can be conservatively abstracted away and the interactions between interconnected devices can be verified using Constraint Logic Programming based on Relational Interval Arithmetic. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method is of interest to readers who are involved in defining methods and tools for system-level design specification and verification. The techniques for interface compatibility verification can be used by practicing designers, without any more sophisticated tool than a calculator.

Model Generation in Electronic Design covers a wide range of model applications and research. The book begins by describing a model generator to create component models. It goes on to discuss ASIC design and ASIC library generation. This section includes chapters on the requirements for developing and ASIC library, a case study in which VITAL is used to create such a library, and the analysis and description of the accuracy required in modeling interconnections in ASIC design. Other chapters describe the development of thermal models for electronic devices, the development of a set of model packages for VHDL floating point operations, a techniques for model validation and verification, and a tool for model encryption. Model Generation in Electronic Design is an essential update for users, vendors, model producers, technical managers, designers and researchers working in electronic design.

VHDL Answers to Frequently asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp. lang. vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error free, and simulation efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complete simulatable examples. TItis book is intended for those who are seeking an enhanced proficiency in VHDL. Its target audience includes: 1. Engineers. The book addresses a set of problems commonly experienced by real users of VHDL. It provides practical explanations to the questions, and suggests practical solutions to the raised issues. It also includes packages of common utilities that are useful in the generation of debug code and testbench designs. These packages include conversions to strings (the IMAGE package), generation of Linear Feedback Shift Registers (LFSR), Multiple Input Shift Register (MISR), and random number generators.

Improvement in the quality of integrated circuit designs and a designer's productivity can be achieved by a combination of two factors: * Using more structured design methodologies for extensive reuse of existing components and subsystems. It seems that 70% of new designs correspond to existing components that cannot be reused because of a lack of methodologies and tools. * Providing higher level design tools allowing to start from a higher level of abstraction. After the success and the widespread acceptance of logic and RTL synthesis, the next step is behavioral synthesis, commonly called architectural or high-level synthesis. Behavioral Synthesis and Component Reuse with VHDL provides methods and techniques for VHDL based behavioral synthesis and component reuse. The goal is to develop VHDL modeling strategies for emerging behavioral synthesis tools. Special attention is given to structured and modular design methods allowing hierarchical behavioral specification and design reuse.The goal of this book is not to discuss behavioral synthesis in general or to discuss a specific tool but to describe the specific issues related to behavioral synthesis of VHDL description. This book targets designers who have to use behavioral synthesis tools or who wish to discover the real possibilities of this emerging technology. The book will also be of interest to teachers and students interested to learn or to teach VHDL based behavioral synthesis.

A Guide to VHDL, Second Edition is intended for the working engineer who needs to develop, document, simulate, and synthesize a design using the VHDL language. It is for system and chip designers who are working with VHDL CAD tools, and who have some experience programming in Fortran, Pascal, or C and have used a logic simulator. A Guide to VHDL, Second Edition includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises included in the chapters can be run to reinforce the learning experience. For practical purposes, this book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. A Guide to VHDL, Second Edition is designed as a primer and its contents are appropriate for an introductory course in VHDL. The VHDL language was updated in 1992 with some minor improvements. In most cases, the language is upward compatible. Although this book is based primarily on the VHDL 1987 standard, this new second edition indicates the significant changes in the 1992 language to assist the designer in writing upwardly compatible code.

The Verilog Programming Language Interface, commonly called the Verilog PU, is one of the more powerful features of Verilog. The PU provides a means for both hardware designers and software engineers to interface their own programs to commercial Verilog simulators. Through this interface, a Verilog simulator can be customized to perform virtually any engineering task desired. Just a few of the common uses of the PU include interfacing Veri log simulations to C language models, adding custom graphical tools to a simulator, reading and writing proprietary file formats from within a simulation, performing test coverage analysis during simulation, and so forth. The applications possible with the Verilog PLI are endless. Intended audience: this book is written for digital design engineers with a background in the Verilog Hardware Description Language and a fundamental knowledge of the C programming language. It is expected that the reader: Has a basic knowledge of hardware engineering, specifically digital design of ASIC and FPGA technologies. Is familiar with the Verilog Hardware Description Language (HDL), and can write models of hardware circuits in Verilog, can write simulation test fixtures in Verilog, and can run at least one Verilog logic simulator. Knows basic C-language programming, including the use of functions, pointers, structures and file I/O. Explanations of the concepts and terminology of digital

A reactive system is one that is in continual interaction with its environment and executes at a pace determined by that environment. Examples of reactive systems are network protocols, air-traffic control systems, industrial-process control systems etc. Reactive systems are ubiquitous and represent an important class of systems. Due to their complex nature, such systems are extremely difficult to specify and implement. Many reactive systems are employed in highly-critical applications, making it crucial that one considers issues such as reliability and safety while designing such systems. The design of reactive systems is considered to be problematic, and p.oses one of the greatest challenges in the field of system design and development. In this paper, we discuss specification-modeling methodologies for reactive systems. Specification modeling is an important stage in reactive system design where the designer specifies the desired properties of the reactive system in the form of a specification model. This specification model acts as the guidance and source for the implementation. To develop the specification model of complex systems in an organized manner, designers resort to specification modeling methodologies. In the context of reactive systems, we can call such methodologies reactive-system specification modeling methodologies.