Control system design is a challenging task for practicing engineers. It requires knowledge of different engineering fields, a good understanding of technical specifications and good communication skills. The current book introduces the reader into practical control system design, bridging the gap between theory and practice. The control design techniques presented in the book are all model based., considering the needs and possibilities of practicing engineers. Classical control design techniques are reviewed and methods are presented how to verify the robustness of the design. It is how the designed control algorithm can be implemented in real-time and tested, fulfilling different safety requirements. Good design practices and the systematic software development process are emphasized in the book according to the generic standard IEC61508. The book is mainly addressed to practicing control and embedded software engineers - working in research and development - as well as graduate students who are faced with the challenge to design control systems and implement them in real-time.

Communication protocols are rules whereby meaningful communication can be exchanged between different communicating entities. In general, they are complex and difficult to design and implement. Specifications of communication protocols written in a natural language (e.g. English) can be unclear or ambiguous, and may be subject to different interpretations. As a result, independent implementations of the same protocol may be incompatible. In addition, the complexity of protocols make them very hard to analyze in an informal way. There is, therefore, a need for precise and unambiguous specification using some formal languages. Many protocol implementations used in the field have almost suffered from failures, such as deadlocks. When the conditions in which the protocols work correctly have been changed, there has been no general method available for determining how they will work under the new conditions. It is necessary for protocol designers to have techniques and tools to detect errors in the early phase of design, because the later in the process that a fault is discovered, the greater the cost of rectifying it. Protocol verification is a process of checking whether the interactions of protocol entities, according to the protocol specification, do indeed satisfy certain properties or conditions which may be either general (e.g., absence of deadlock) or specific to the particular protocol system directly derived from the specification. In the 80s, an ISO (International Organization for Standardization) working group began a programme of work to develop formal languages which were suitable for Open Systems Interconnection (OSI). This group called such languages Formal Description Techniques (FDTs). Some of the objectives of ISO in developing FDTs were: enabling unambiguous, clear and precise descriptions of OSI protocol standards to be written, and allowing such specifications to be verified for correctness. There are two FDTs standardized by ISO: LOTOS and Estelle. Communication Protocol Specification and Verification is written to address the two issues discussed above: the needs to specify a protocol using an FDT and to verify its correctness in order to uncover specification errors in the early stage of a protocol development process. The readership primarily consists of advanced undergraduate students, postgraduate students, communication software developers, telecommunication engineers, EDP managers, researchers and software engineers. It is intended as an advanced undergraduate or postgraduate textbook, and a reference for communication protocol professionals.

The proliferation and growth of Electronic Design Automation (EDA) has spawned many diverse and interesting technologies. One of the most prominent of these technologies is the VHSIC Hardware Description Language, or VHDL. VHDL permits designers of digital modules, components, systems, and even networks to describe their designs both structurally and behaviorally. VHDL also allows simulation of the designs in order to investigate their performance prior to actually implementing them in hardware. Having gained the ability to simulate designs once encoded in VHDL, designers were naturally confronted with the issue of testing these designs. VHDL did not explicitly address the requirement to insert particular digital waveforms, often termed test vectors or patterns, or to subsequently assess the correctness of the response from some digital entity. In a distributed design environment, or even in an isolated one where the design was subject to review or scrutiny by another organization, de-facto methods of testing and evaluating results proved faulty. The reason was a lack of standardization.When organization A designed a circuit and tested it with their self-developed test tools it had a certain behavior. When it was delivered to organization B and B tested it using their test tools, the behavior was different. Was the fault in the circuit, in A's tools, or in B's tools? The only way to resolve this was for both organizations to agree on a test apparatus, validate its correctness and use it consistently. While VHDL was an IEEE standard language, and consistency among myriad designers was fairly well guaranteed, no such standard existed for test waveform generation and assessment. Hence, the value of standardization in the design language was being negated by the lack of such a standard for testing. The Waveform and Vector Exchange Specification, or WAVES, was conceived and designed to solve this testing problem -- and it has. Being both a subset of VHDL itself, as well as an IEEE standard, it guarantees both conformity among multiple applications and easy integration with VHDL units under test (UUTs). Using WAVES and VHDL for Effective Design and Testing will serve many purposes.For the WAVES beginner, its tutorial will make the application of WAVES in typical, standard usage straightforward and convenient. For the more advanced user, the advanced topics will provide insight into the nuances of these useful capabilities. For all users, the tools, templates and examples given in the chapters, as well as on the companion disk, will provide a practical starting foundation for using WAVES and VHDL.

The arrival and popularity of multi-core processors has sparked a renewed interest in the development of parallel programs. Similarly, the availability of low-cost microprocessors and sensors has generated a great interest in embedded real-time programs. This book provides students and programmers whose backgrounds are in traditional sequential programming with the opportunity to expand their capabilities into parallel, embedded, real-time and distributed computing. It also addresses the theoretical foundation of real-time scheduling analysis, focusing on theory that is useful for actual applications. Written by award-winning educators at a level suitable for undergraduates and beginning graduate students, this book is the first truly entry-level textbook in the subject. Complete examples allow readers to understand the context in which a new concept is used, and enable them to build and run the examples, make changes, and observe the results.

Verilog(R) Quickstart is a basic, practical, introductory textbook for professionals and students alike. This book explains how a designer can be more effective through the use of the Verilog hardware description language to simulate and document a design. By understanding simulation, a designer can simulate a design to see if a design works before it is built. This gives the designer an opportunity to try different ideas. Documentation allows a designer to maintain and reuse a design more easily. Verilog's intrinsic hierarchical modularity enables the designer to easily reuse portions of the design as 'intellectual property' or 'macro-cells'. Verilog(R) Quickstart presents some of the formal Verilog syntax and definitions and then shows practical uses. This book does not oversimplify the Verilog language nor does it emphasize theory. Verilog(R) Quickstart has over 100 examples that are used to illustrate aspects of the language. In the later chapters the focus is on working with modeling style and explaining why and when one would use different elements of the language. Another feature of the book is the chapter on state machine modeling.There is also a chapter on test benches and testing strategy as well as a chapter on debugging. Verilog(R) Quickstart is designed to teach the Verilog language, to show the designer how to model in Verilog and to explain the basics of using Verilog simulators.

A Guide to VHDL is intended for the working engineer who needs to develop, document, simulate and synthesize a design using the VHDL language. It is for system and chip designers who are working with VHDL CAD tools, and who have some experience programming in Fortran, Pascal, or C and have used a logic simulator. A Guide to VHDL includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises invluded in the chapters can be run to reinforce the learning experience. For practical purposes, this book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. A Guide to VHDL can be used as a primer, since its contents are appropriate for an introductory course in VHDL.

Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process. The intended audience for Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.

Physicians, lawyers, engineers, architects, financial analysts, and other pro fessionals articulate an increasing need for support by intelligent workstations for decision making, analysis, communication, and other activities. "Intelligent Workstations for Professionals" is the collection of papers presented by inter national scientists at a symposium and workshop in March 1992. Requirements from potential users, studies of their behavior as well as approaches and aspects oftechnical realizations of "intelligent" functions are introduced. Eight contributions from members of the Center for Information and Tele communication Technology (Clrn of Northwestern University, Wisconsin Whitewater University, and the Children's Memorial Hospital deal with the latest findings of the UNIS (Users' Needs for Intelligent Systems) project, which is designed to identify needs and wishes from professionals for intelligent sup port systems and the potential barriers to adoption and use of such systems. The remaining papers concentrate on new approaches and techniques that en hance the "intelligence" of future workstations. They tackle issues like architectural trends in workstation design, the combination of workstations with HDTV and speech processing, automatic reading and understanding of documents, the automated development of software, or the processing of in exact knowledge. These papers were contributed by members of the DFKI GmbH (German Research Institute for Artificial Intelligence), GMD mbH (German Society for Mathematics and Data Processing), Siemens Gammasonics Inc., Siemens Nixdorf Informationssysteme AG and Siemens AG."

th This volume gathers together the technical papers presented at the 8 European Conference on Computer Supported Cooperative Work (ECSCW), held in Helsinki Finland. ECSCW is an international forum for multidisciplinary research covering the technical, empirical, and theoretical aspects of collaboration and computer systems. The 20 papers presented here have been selected via a rigorous reviewing process from 110 submissions. Both the number of submissions and the quality of the selected papers are testimony to the diversity and energy of the CSCW community. We trust that you will find the papers interesting and that they will serve to stimulate further quality work within the community. The technical papers are complemented by a wider set of activities at ECSCW 2003, including tutorials, workshops, demonstrations, videos, posters and a doctoral colloquium. Together these provide rich opportunities for discussion, learning and exploration of the more recent and novel issues in the field. This conference could not have taken place without considerable enthusiasm, support and participation, not to mention the hard work of a number of people. In particular, we would like to thank the following: * The authors, representing over 17 countries and 97 institutions, who submitted a paper. So many submissions of such high quality are the basis of a good conference. * The members of the program committee who so diligently reviewed and discussed papers. Their collective decisions result in a good scientific program and their feedback to authors strengthens the work of the community.

Speech technology - the use of speech as a means of sending information to, and receiving information from computer systems has been in use as a research tool for many years. Only recently has it begun to move out of the laboratory and into commercially worthwhile applications, first with compressed and synthesised spoken messages, then with computer recognition of spoken messages, and today with diverse applications involving both recognition and reproduction of human speech. We have written this book because we believe the technology has now advanced to the point where many more applications of voice recognition and response are both feasible and economically attractive. Computers that can understand everyday speech are still a distant prospect, but provided the limitations of present day equipment are clearly understood there is much that can be achieved with it. Our aim is to show, in non-technical language, what is now possible with the help of speech technology. The text includes many examples of current applications in industry, commerce and other fields, and we have selected five current industrial applications combining speech recognition and response for more detailed attention. Industrial cases have been chosen both because we see industry as an important growth area for speech applications in the next few years, and because it presents some of the greatest difficulties in speech recognition - if you can make it work in industry, then you can make it work almost anywhere."

Based on the highly successful second edition, this extended edition of "SystemVerilog for Verification: A Guide to Learning the Testbench Language Features" teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill.

In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features, including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students' understanding of the material. Other features of this revision include: New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standardDescriptions of UVM features such as factories, the test registry, and the configuration databaseExpanded code samples and explanations Numerous samples that have been tested on the major SystemVerilog simulators

"SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition "is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.
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The great advances made in large-scale integration of semiconductors and the resulting cost-effective digital processors and data storage devices determine the present development of automation. The application of digital techniques to process automation started in about 1960, when the first process computer was installed. From about 1970 process computers with cathodic ray tube display have become standard equipment for larger automation systems. Until about 1980 the annual increase of process computers was about 20 to 30%. The cost of hardware has already then shown a tendency to decrease, whereas the relative cost of user software has tended to increase. Because of the high total cost the first phase of digital process automation is characterized by the centralization of many functions in a single (though sometimes in several) process computer. Application was mainly restricted to medium and large processes. Because of the far-reaching consequences of a breakdown in the central computer parallel standby computers or parallel back-up systems had to be provided. This meant a substantial increase in cost. The tendency to overload the capacity and software problems caused further difficulties. In 1971 the first microprocessors were marketed which, together with large-scale integrated semiconductor memory units and input/output modules, can be assem bled into cost-effective microcomputers. These microcomputers differ from process computers in fewer but higher integrated modules and in the adaptability of their hardware and software to specialized, less comprehensive tasks."

The Verilog Programming Language Interface, commonly called the Verilog PU, is one of the more powerful features of Verilog. The PU provides a means for both hardware designers and software engineers to interface their own programs to commercial Verilog simulators. Through this interface, a Verilog simulator can be customized to perform virtually any engineering task desired. Just a few of the common uses of the PU include interfacing Veri log simulations to C language models, adding custom graphical tools to a simulator, reading and writing proprietary file formats from within a simulation, performing test coverage analysis during simulation, and so forth. The applications possible with the Verilog PLI are endless. Intended audience: this book is written for digital design engineers with a background in the Verilog Hardware Description Language and a fundamental knowledge of the C programming language. It is expected that the reader: Has a basic knowledge of hardware engineering, specifically digital design of ASIC and FPGA technologies. Is familiar with the Verilog Hardware Description Language (HDL), and can write models of hardware circuits in Verilog, can write simulation test fixtures in Verilog, and can run at least one Verilog logic simulator. Knows basic C-language programming, including the use of functions, pointers, structures and file I/O. Explanations of the concepts and terminology of digital

Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplishment, have you ever had someone ask you, "Are you good or are you just lucky?"? Many design projects depend on blind luck in hopes that the chip will work. Other's, just adamantly rely on their own abilities to bring the chip to success. ill either case, how can we tell the difference between being good or lucky? There must be a better way not to fail. Failure. No one likes to fail. ill his book, "The Logic of Failure", Dietrich Domer argues that failure does not just happen. A series of wayward steps leads to disaster. Often these wayward steps are not really logical, decisive steps, but more like default omissions. Anti-planning if you will, an ad-hoc approach to doing something. To not plan then, is to fail.

The Verilog language is a hardware description language which provides a means of specifying a digital system at a wide range of levels of abstraction. The language supports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of a description. Verilog was originally designed in the winter of 1983/84 as a proprietary verification/simulation product. Since then, several other proprietary analysis tools have been developed around the language, including a fault simulator and a timing analyzer; the language being instrumental in providing consistency across these tools. Now, the language is openly available for any tool to read and write. This book introduces the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Where possible, we have stayed away from simulator-specific details and concentrated on design specification, but have included enough information to be able to have working executable models. The book takes a tutorial approach to presenting the language.

Hardware description languages (HDL) such as VHDL and Verilog have found their way into almost every aspect of the design of digital hardware systems. Since their inception they gradually proved to be an essential part of modern design methodologies and design automation tools, ever exceeding their original goals of being description and simulation languages. Their use for automatic synthesis, formal proof, and testing are good examples. So far, HDLs have been mainly dealing with digital systems. However, integrated systems designed today require more and more analog parts such as A/D and D/A converters, phase locked loops, current mirrors, etc. The verification of the complete system therefore asks for the use of a single language. Using VHDL or Verilog to handle analog descriptions is possible, as it is shown in this book, but the real power is coming from true mixed-signal HDLs that integrate discrete and continuous semantics into a unified framework. Analog HDLs (AHDL) are considered here a subset of mixed-signal HDLs as they intend to provide the same level of features as HDLs do but with a scope limited to analog systems, possibly with limited support of discrete semantics. Analog and Mixed-Signal Hardware Description Languages covers several aspects related to analog and mixed-signal hardware description languages including: The use of a digital HDL for the description and the simulation of analog systems The emergence of extensions of existing standard HDLs that provide true analog and mixed-signal HDLs. The use of analog and mixed-signal HDLs for the development of behavioral models of analog (electronic) building blocks (operational amplifier, PLL) and for the design of microsystems that do not only involve electronic parts. The use of a front-end tool that eases the description task with the help of a graphical paradigm, yet generating AHDL descriptions automatically. Analog and Mixed-Signal Hardware Description Languages is the first book to show how to use these new hardware description languages in the design of electronic components and systems. It is necessary reading for researchers and designers working in electronic design.

by Phil Moorby The Verilog Hardware Description Language has had an amazing impact on the mod em electronics industry, considering that the essential composition of the language was developed in a surprisingly short period of time, early in 1984. Since its introduc tion, Verilog has changed very little. Over time, users have requested many improve ments to meet new methodology needs. But, it is a complex and time consuming process to add features to a language without ambiguity, and maintaining consistency. A group of Verilog enthusiasts, the IEEE 1364 Verilog committee, have broken the Verilog feature doldrums. These individuals should be applauded. They invested the time and energy, often their personal time, to understand and resolve an extensive wish-list of language enhancements. They took on the task of choosing a feature set that would stand up to the scrutiny of the standardization process. I would like to per sonally thank this group. They have shown that it is possible to evolve Verilog, rather than having to completely start over with some revolutionary new language. The Verilog 1364-2001 standard provides many of the advanced building blocks that users have requested. The enhancements include key components for verification, abstract design, and other new methodology capabilities. As designers tackle advanced issues such as automated verification, system partitioning, etc., the Verilog standard will rise to meet the continuing challenge of electronics design.

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available. These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs.

Standardization of hardware description languages and the availability of synthesis tools has brought about a remarkable increase in the productivity of hardware designers. Yet design verification methods and tools lag behind and have difficulty in dealing with the increasing design complexity. This may get worse because more complex systems are now constructed by (re)using Intellectual Property blocks developed by third parties. To verify such designs, abstract models of the blocks and the system must be developed, with separate concerns, such as interface communication, functionality, and timing, that can be verified in an almost independent fashion. Standard Hardware Description Languages such as VHDL and Verilog are inspired by procedural `imperative' programming languages in which function and timing are inherently intertwined in the statements of the language. Furthermore, they are not conceived to state the intent of the design in a simple declarative way that contains provisions for design choices, for stating assumptions on the environment, and for indicating uncertainty in system timing. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method presents a description methodology that was inspired by Timing Diagrams and Process Algebras, the so-called Hierarchical Annotated Diagrams. It is suitable for specifying systems with complex interface behaviors that govern the global system behavior. A HADD specification can be converted into a behavioral real-time model in VHDL and used to verify the surrounding logic, such as interface transducers. Also, function can be conservatively abstracted away and the interactions between interconnected devices can be verified using Constraint Logic Programming based on Relational Interval Arithmetic. Hierarchical Annotated Action Diagrams: An Interface-Oriented Specification and Verification Method is of interest to readers who are involved in defining methods and tools for system-level design specification and verification. The techniques for interface compatibility verification can be used by practicing designers, without any more sophisticated tool than a calculator.

Improvement in the quality of integrated circuit designs and a designer's productivity can be achieved by a combination of two factors: * Using more structured design methodologies for extensive reuse of existing components and subsystems. It seems that 70% of new designs correspond to existing components that cannot be reused because of a lack of methodologies and tools. * Providing higher level design tools allowing to start from a higher level of abstraction. After the success and the widespread acceptance of logic and RTL synthesis, the next step is behavioral synthesis, commonly called architectural or high-level synthesis. Behavioral Synthesis and Component Reuse with VHDL provides methods and techniques for VHDL based behavioral synthesis and component reuse. The goal is to develop VHDL modeling strategies for emerging behavioral synthesis tools. Special attention is given to structured and modular design methods allowing hierarchical behavioral specification and design reuse.The goal of this book is not to discuss behavioral synthesis in general or to discuss a specific tool but to describe the specific issues related to behavioral synthesis of VHDL description. This book targets designers who have to use behavioral synthesis tools or who wish to discover the real possibilities of this emerging technology. The book will also be of interest to teachers and students interested to learn or to teach VHDL based behavioral synthesis.

VHDL Answers to Frequently asked Questions is a follow-up to the author's book VHDL Coding Styles and Methodologies (ISBN 0-7923-9598-0). On completion of his first book, the author continued teaching VHDL and actively participated in the comp. lang. vhdl newsgroup. During his experiences, he was enlightened by the many interesting issues and questions relating to VHDL and synthesis. These pertained to: misinterpretations in the use of the language; methods for writing error free, and simulation efficient, code for testbench designs and for synthesis; and general principles and guidelines for design verification. As a result of this wealth of public knowledge contributed by a large VHDL community, the author decided to act as a facilitator of this information by collecting different classes of VHDL issues, and by elaborating on these topics through complete simulatable examples. TItis book is intended for those who are seeking an enhanced proficiency in VHDL. Its target audience includes: 1. Engineers. The book addresses a set of problems commonly experienced by real users of VHDL. It provides practical explanations to the questions, and suggests practical solutions to the raised issues. It also includes packages of common utilities that are useful in the generation of debug code and testbench designs. These packages include conversions to strings (the IMAGE package), generation of Linear Feedback Shift Registers (LFSR), Multiple Input Shift Register (MISR), and random number generators.

A Guide to VHDL, Second Edition is intended for the working engineer who needs to develop, document, simulate, and synthesize a design using the VHDL language. It is for system and chip designers who are working with VHDL CAD tools, and who have some experience programming in Fortran, Pascal, or C and have used a logic simulator. A Guide to VHDL, Second Edition includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises included in the chapters can be run to reinforce the learning experience. For practical purposes, this book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. A Guide to VHDL, Second Edition is designed as a primer and its contents are appropriate for an introductory course in VHDL. The VHDL language was updated in 1992 with some minor improvements. In most cases, the language is upward compatible. Although this book is based primarily on the VHDL 1987 standard, this new second edition indicates the significant changes in the 1992 language to assist the designer in writing upwardly compatible code.

The purpose of the 12th Conference Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing (SNPD 2011) held on July 6-8, 2011 in Sydney, Australia was to bring together scientists, engineers, computer users, and students to share their experiences and exchange new ideas and research results about all aspects (theory, applications and tools) of computer and information sciences, and to discuss the practical challenges encountered along the way and the solutions adopted to solve them.

The conference organizers selected 14 outstanding papers from SNPD 2011, all of which you will find in this volume of Springer s Studies in Computational Intelligence. "

A reactive system is one that is in continual interaction with its environment and executes at a pace determined by that environment. Examples of reactive systems are network protocols, air-traffic control systems, industrial-process control systems etc. Reactive systems are ubiquitous and represent an important class of systems. Due to their complex nature, such systems are extremely difficult to specify and implement. Many reactive systems are employed in highly-critical applications, making it crucial that one considers issues such as reliability and safety while designing such systems. The design of reactive systems is considered to be problematic, and p.oses one of the greatest challenges in the field of system design and development. In this paper, we discuss specification-modeling methodologies for reactive systems. Specification modeling is an important stage in reactive system design where the designer specifies the desired properties of the reactive system in the form of a specification model. This specification model acts as the guidance and source for the implementation. To develop the specification model of complex systems in an organized manner, designers resort to specification modeling methodologies. In the context of reactive systems, we can call such methodologies reactive-system specification modeling methodologies.