This book presents three approaches to the analysis of the deadline miss ratio of applications with stochastic task execution times. Each best fits a different context: an exact one efficiently applicable to monoprocessor systems; an approximate one, which allows for designer-controlled trade-off between analysis accuracy and analysis speed; and one less accurate but sufficiently fast in order to be placed inside optimization loops.

Both authors have taught the course of "Distributed Systems" for many years in the respective schools. During the teaching, we feel strongly that "Distributed systems" have evolved from traditional "LAN" based distributed systems towards "Internet based" systems. Although there exist many excellent textbooks on this topic, because of the fast development of distributed systems and network programming/protocols, we have difficulty in finding an appropriate textbook for the course of "distributed systems" with orientation to the requirement of the undergraduate level study for today's distributed technology. Specifically, from - to-date concepts, algorithms, and models to implementations for both distributed system designs and application programming. Thus the philosophy behind this book is to integrate the concepts, algorithm designs and implementations of distributed systems based on network programming. After using several materials of other textbooks and research books, we found that many texts treat the distributed systems with separation of concepts, algorithm design and network programming and it is very difficult for students to map the concepts of distributed systems to the algorithm design, prototyping and implementations. This book intends to enable readers, especially postgraduates and senior undergraduate level, to study up-to-date concepts, algorithms and network programming skills for building modern distributed systems. It enables students not only to master the concepts of distributed network system but also to readily use the material introduced into implementation practices.

This book constitutes the refereed proceedings of the 19th CCF Conference on Computer Engineering and Technology, NCCET 2015, held in Hefei, China, in October 2015. The 18 papers presented were carefully reviewed and selected from 158 submissions. They are organized in topical sections on processor architecture; application specific processors; computer application and software optimization; technology on the horizon.

This book describes the emerging field of self-organizing, multicore, distributed and real-time embedded systems. Self -organization of both hardware and software can be a key technique to handle the growing complexity of modern computing systems. Distributed systems running hundreds of tasks on dozens of processors, each equipped with multiple cores, requires self-organization principles to ensure efficient and reliable operation. This book addresses various, so-called Self-X features such as self-configuration, self-optimization, self-adaptation, self-healing and self-protection.

This book serves a dual purpose: firstly to combine the treatment of circuits and digital electronics, and secondly, to establish a strong connection with the contemporary world of digital systems. The need for this approach arises from the observation that introducing digital electronics through a course in traditional circuit analysis is fast becoming obsolete. Our world has gone digital. Automata theory helps with the design of digital circuits such as parts of computers, telephone systems and control systems. A complete perspective is emphasized, because even the most elegant computer architecture will not function without adequate supporting circuits. The focus is on explaining the real-world implementation of complete digital systems. In doing so, the reader is prepared to immediately begin design and implementation work. This work serves as a bridge to take readers from the theoretical world to the everyday design world where solutions must be complete to be successful.

It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification. Functional errors manifest themselves very early in the design flow, and unless they are detected up front, they can result in severe consequence- both financially and from a safety viewpoint. Indeed, several recent instances of high-profile functional errors (e. g. , the Pentium FDIV bug) have resulted in - creased attention paid to verifying the functional correctness of designs. Recent efforts have proposed augmenting the traditional RTL simulation-based validation methodology with formal techniques in an attempt to uncover hard-to-find c- ner cases, with the goal of trying to reach RTL functional verification closure. However, what is often not highlighted is the fact that in spite of the tremendous time and effort put into such efforts at the RTL and lower levels of abstraction, the complexity of contemporary embedded systems makes it difficult to guarantee functional correctness at the system level under all possible operational scenarios. The problem is exacerbated in current System-on-Chip (SOC) design meth- ologies that employ Intellectual Property (IP) blocks composed of processor cores, coprocessors, and memory subsystems. Functional verification becomes one of the major bottlenecks in the design of such systems.

This textbook serves as an introduction to the subject of embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions. Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which will make the material in this book applicable to a greater number of courses where these tools are already in use. More examples and exercises have been added throughout the book. "If I were teaching a course on this subject, I would use this as a resource and text. If I were a student who wanted to learn codesign, I would look for a course that at least used a similar approach. If I were an engineer or engineering manager who wanted to learn more about codesign from a very practical perspective, I would read this book first before any other. When I first started learning about codesign as a practitioner, a book like this would have been the perfect introduction." --Grant Martin, Tensilica--

This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects. The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages: Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT); Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly; Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model; Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.

This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade. Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems. This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of, and trust in, modern society's microelectronic-supported infrastructures.

A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.

This book introduces a novel design methodology which can significantly reduce the ASIP development effort through high degrees of design automation. The key elements of this new design methodology are a powerful application profiler and an automated instruction-set customization tool which considerably lighten the burden of mapping a target application to an ASIP architecture in the initial design stages. The book includes several design case studies with real life embedded applications to demonstrate how the methodology and the tools can be used in practice for accelerating the overall ASIP design process.

Dynamic Reconfigurable Architectures and Transparent Optimization Techniques presents a detailed study on new techniques to cope with the aforementioned limitations. First, characteristics of reconfigurable systems are discussed in details, and a large number of case studies is shown. Then, a detailed analysis of several benchmarks demonstrates that such architectures need to attack a diverse range of applications with very different behaviours, besides supporting code compatibility. This requires the use of dynamic optimization techniques, such as Binary Translation and Trace reuse. Finally, works that combine both reconfigurable systems and dynamic techniques are discussed and a quantitative analysis of one them, the DIM architecture, is presented.

Platform Based Design at the Electronic System Level presents a multi-faceted view of the challenges facing the electronic industry in the development and integration of complex heterogeneous systems, including both hardware and software components. It analyses and proposes solutions related to the provision of integration platforms by System on Chip and Integrated Platform providers in light of the needs and requirements expressed by the system companies: they are the users of such platforms, which they apply to develop their next-generation products. This is the first book to examine ESL from perspectives of system developer, platform provider and Electronic Design Automation.

Speech Processing has rapidly emerged as one of the most widespread and well-understood application areas in the broader discipline of Digital Signal Processing. Besides the telecommunications applications that have hitherto been the largest users of speech processing algorithms, several non-traditional embedded processor applications are enhancing their functionality and user interfaces by utilizing various aspects of speech processing. "Speech Processing in Embedded Systems" describes several areas of speech processing, and the various algorithms and industry standards that address each of these areas. The topics covered include different types of Speech Compression, Echo Cancellation, Noise Suppression, Speech Recognition and Speech Synthesis. In addition this book explores various issues and considerations related to efficient implementation of these algorithms on real-time embedded systems, including the role played by processor CPU and peripheral functionality.

In the past decades, the mainstream of microelectronics progression was mainly powered by Moore's law focusing on IC miniaturization down to nano scale. However, there is a fast increasing need for "More than Moore" (MtM) products and technology that are based upon or derived from silicon technologies, but do not simply scale with Moore's law. This book provides new vision, strategy and guidance for the future technology and business development of micro/nanoelectronics.

Production Grids in Asia: Applications, Developments and Global Ties, an edited volume, is based on ISGC (International Symposium on Grid Computing), one of the most prestigious annual events in Asia. It brings together scientists and engineers worldwide to exchange ideas, present challenges/solutions, and introduce future development in the field of Grid Computing. ISGC 2008 was held at Academia Sinica, Taipei, Taiwan in April 2008. The edited proceedings present international projects in Grid operation, Grid Middleware and e-Science applications. Leading Grid projects from Asia-Pacific are also covered. Production Grids in Asia: Applications, Developments and Global Ties is designed for a professional audience composed of industry researchers and practitioners within the Grid community. This volume is also suitable for advanced-level students in computer science.

Electronic System Level Design: an Open-Source Approach is based on the successful experience acquired with the conception of the ADL ArchC, the development of its underlying tool suite, and the building of its platform modeling infrastructure. With more than 10000 accesses per year since 2004, the dissemination of ArchC models reached not only students in quest of proper infrastructure to develop their research projects but also some companies in need of processor models to build virtual platforms using SystemC. The need to anticipate the development of hardware-dependent software and to build virtual prototypes gave rise to Transaction Level Modeling (TLM). Since SystemC provided the elements and the adequate abstraction level for supporting TLM, their relation has grown so strong that OSCI created a TLM Working Group whose effort resulted in the recently released TLM 2.0 standard, which is also covered in this book.

Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.

This book describes a model-based development approach for globally-asynchronous locally-synchronous distributed embedded controllers. This approach uses Petri nets as modeling formalism to create platform and network independent models supporting the use of design automation tools. To support this development approach, the Petri nets class in use is extended with time-domains and asynchronous-channels. The authors' approach uses models not only providing a better understanding of the distributed controller and improving the communication among the stakeholders, but also to be ready to support the entire lifecycle, including the simulation, the verification (using model-checking tools), the implementation (relying on automatic code generators), and the deployment of the distributed controller into specific platforms. Uses a graphical and intuitive modeling formalism supported by design automation tools; Enables verification, ensuring that the distributed controller was correctly specified; Provides flexibility in the implementation and maintenance phases to achieve desired constraints (high performance, low power consumption, reduced costs), enabling porting to different platforms using different communication nodes, without changing the underlying behavioral model.

This is the first book to focus on designing run-time reconfigurable systems on FPGAs, in order to gain resource and power efficiency, as well as to improve speed. Case studies in partial reconfiguration guide readers through the FPGA jungle, straight toward a working system. The discussion of partial reconfiguration is comprehensive and practical, with models introduced together with methods to implement efficiently the corresponding systems. Coverage includes concepts for partial module integration and corresponding communication architectures, floorplanning of the on-FPGA resources, physical implementation aspects starting from constraining primitive placement and routing all the way down to the bitstream required to configure the FPGA, and verification of reconfigurable systems.

This book provides step-by-step guidance on how to design VLSI systems using Verilog. It shows the way to design systems that are device, vendor and technology independent. Coverage presents new material and theory as well as synthesis of recent work with complete Project Designs using industry standard CAD tools and FPGA boards. The reader is taken step by step through different designs, from implementing a single digital gate to a massive design consuming well over 100,000 gates. All the design codes developed in this book are Register Transfer Level (RTL) compliant and can be readily used or amended to suit new projects.

This book constitutes the refereed proceedings of the 6th International Conference on Reversible Computation, RC 2014, held in Kyoto, Japan, in July 2014. The 14 contributions presented together with three invited talks were carefully reviewed and selected from 27 submissions. The papers are organized in topical sections on automata for reversible computation; notation and languages for reversible computation; synthesis and optimization for reversible circuits; validation and representation of quantum logic.

This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions. The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost.

This book presents a new FPGA architecture known as tree-based FPGA architecture, due to its hierarchical nature. This type of architecture has been relatively unexplored despite their better performance and predictable routing behavior, as compared to mesh-based FPGA architectures. In this book, we explore and optimize the tree-based architecture and we evaluate it by comparing it to equivalent mesh-based FPGA architectures.

Dynamically Reconfigurable Systems is the first ever to focus on the emerging field of Dynamically Reconfigurable Computing Systems. While programmable logic and design-time configurability are well elaborated and covered by various texts, this book presents a unique overview over the state of the art and recent results for dynamic and run-time reconfigurable computing systems. Reconfigurable hardware is not only of utmost importance for large manufacturers and vendors of microelectronic devices and systems, but also a very attractive technology for smaller and medium-sized companies. Hence, Dynamically Reconfigurable Systems also addresses researchers and engineers actively working in the field and provides them with information on the newest developments and trends in dynamic and run-time reconfigurable systems.