Leaf Cell and Hierarchical Compaction Techniques presents novel algorithms developed for the compaction of large layouts. These algorithms have been implemented as part of a system that has been used on many industrial designs. The focus of Leaf Cell and Hierarchical Compaction Techniques is three-fold. First, new ideas for compaction of leaf cells are presented. These cells can range from small transistor-level layouts to very large layouts generated by automatic Place and Route tools. Second, new approaches for hierarchical pitchmatching compaction are described and the concept of a Minimum Design is introduced. The system for hierarchical compaction is built on top of the leaf cell compaction engine and uses the algorithms implemented for leaf cell compaction in a modular fashion. Third, a new representation for designs called Virtual Interface, which allows for efficient topological specification and representation of hierarchical layouts, is outlined. The Virtual Interface representation binds all of the algorithms and their implementations for leaf and hierarchical compaction into an intuitive and easy-to-use system. From the Foreword: ...In this book, the authors provide a comprehensive approach to compaction based on carefully conceived abstractions. They describe the design of algorithms that provide true hierarchical compaction based on linear programming, but cut down the complexity of the computations through introduction of innovative representations that capture the provably minimum amount of required information needed for correct compaction. In most compaction algorithms, the complexity goes up with the number of design objects, but in this approach, complexity is due to the irregularity of the design, and hence is often tractable for most designs which incorporate substantial regularity. Here the reader will find an elegant treatment of the many challenges of compaction, and a clear conceptual focus that provides a unified approach to all aspects of the compaction task...' Jonathan Allen, Massachusetts Institute of Technology

Computer-Aided Design of Analog Circuits and Systems brings together in one place important contributions and state-of-the-art research results in the rapidly advancing area of computer-aided design of analog circuits and systems. This book serves as an excellent reference, providing insights into some of the most important issues in the field.

The Integrated Circuit (IC) industry has gone without a standardized verification approach for decades. This book defines a uniform, standardizable methodology for verifying the logical behavior of an integrated circuit, whether an I/O controller, a microprocessor, or a complete digital system. This book will help Engineers and managers responsible for IC development to bring a single, standards-based methodology to their R & D efforts, cutting costs and improving results.

Physical Design for Multichip Modules collects together a large body of important research work that has been conducted in recent years in the area of Multichip Module (MCM) design. The material consists of a survey of published results as well as original work by the authors. All major aspects of MCM physical design are discussed, including interconnect analysis and modeling, system partitioning and placement, and multilayer routing. For readers unfamiliar with MCMs, this book presents an overview of the different MCM technologies available today. An in-depth discussion of various recent approaches to interconnect analysis are also presented. Remaining chapters discuss the problems of partitioning, placement, and multilayer routing, with an emphasis on timing performance. For the first time, data from a wide range of sources is integrated to present a clear picture of a new, challenging and very important research area. For students and researchers looking for interesting research topics, open problems and suggestions for further research are clearly stated. Points of interest include: Clear overview of MCM technology and its relationship to physical design; Emphasis on performance-driven design, with a chapter devoted to recent techniques for rapid performance analysis and modeling of MCM interconnects; Different approaches to multilayer MCM routing collected together and compared for the first time; Explanation of algorithms is not overly mathematical, yet is detailed enough to give readers a clear understanding of the approach; Quantitative data provided wherever possible for comparison of different approaches; A comprehensive list of references to recent literature on MCMs provided.

This title introduces state-of-the-art design principles for SOI circuit design, and is primarily concerned with circuit-related issues. It considers SOI material in terms of implementation that is promising or has been used elsewhere in circuit development, with historical perspective where appropriate.

This book describes a novel approach for the design of embedded systems and industrial automation systems, using a unified model-driven approach that is applicable in both domains. The authors illustrate their methodology, using the IEC 61499 standard as the main vehicle for specification, verification, static timing analysis and automated code synthesis. The well-known synchronous approach is used as the main vehicle for defining an unambiguous semantics that ensures determinism and deadlock freedom. The proposed approach also ensures very efficient implementations either on small-scale embedded devices or on industry-scale programmable automation controllers (PACs). It can be used for both centralized and distributed implementations. Significantly, the proposed approach can be used without the need for any run-time support. This approach, for the first time, blurs the gap between embedded systems and automation systems and can be applied in wide-ranging applications in automotive, robotics, and industrial control systems. Several realistic examples are used to demonstrate for readers how the methodology can enable them to reduce the time-to-market, while improving the design quality and productivity.

Modern consumers carry many electronic devices, like a mobile phone, digital camera, GPS, PDA and an MP3 player. The functionality of each of these devices has gone through an important evolution over recent years, with a steep increase in both the number of features as in the quality of the services that they provide. However, providing the required compute power to support (an uncompromised combination of) all this functionality is highly non-trivial. Designing processors that meet the demanding requirements of future mobile devices requires the optimization of the embedded system in general and of the embedded processors in particular, as they should strike the correct balance between flexibility, energy efficiency and performance. In general, a designer will try to minimize the energy consumption (as far as needed) for a given performance, with a sufficient flexibility. However, achieving this goal is already complex when looking at the processor in isolation, but, in reality, the processor is a single component in a more complex system. In order to design such complex system successfully, critical decisions during the design of each individual component should take into account effect on the other parts, with a clear goal to move to a global Pareto optimum in the complete multi-dimensional exploration space.

In the complex, global design of battery-operated embedded systems, the focus of Ultra-Low Energy Domain-Specific Instruction-Set Processors is on the energy-aware architecture exploration of domain-specific instruction-set processors and the co-optimization of the datapath architecture, foreground memory, and instruction memory organisation with a link to the required mapping techniques or compiler steps at the early stages of the design. By performing an extensive energy breakdown experiment for a complete embedded platform, both energy and performance bottlenecks have been identified, together with the important relations between the different components. Based on this knowledge, architecture extensions are proposed for all the bottlenecks.

One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufacturing process and by designing the process and the circuits in such a way as to minimize the effect of the inherent variations of the process on performance. The latter is typically referred to as "design for manufacture" or "statistical design." As device sizes continue to shrink, the effects of the inherent fluctuations in the IC fabrication process will have an even more obvious effect on circuit performance. And design for manufacture will increase in importance. We have been working in the area of statistically based computer aided design for more than 13 years. During the last decade we have been working with each other, and individually with our students, to develop methods and CAD tools that can be used to improve yield during the design and manufacturing phases of IC realization. This effort has resulted in a large number of publications that have appeared in a variety of journals and conference proceedings. Thus our motivation in writing this book is to put, in one place, a description of our approach to IC yield enhancement. While the work that is contained in this book has appeared in the open literature, we have attempted to use a consistent notation throughout this book.

When confronted with the hows and whys of nature's computational engines, some prefer to focus upon neural function: addressing issues of neural system behavior and its relation to natural intelligence. Then there are those who prefer the study of the "mechanics" of neural systems: the nuts and bolts of the "wetware": the neurons and synapses. Those who investigate pulse coded implementations ofartificial neural networks know what it means to stand at the boundary which lies between these two worlds: not just asking why natural neural systems behave as they do, but also how they achieve their marvelous feats. The research results presented in this book not only address more conventional abstract notions of neural-like processing, but also the more specific details ofneural-like processors. It has been established for some time that natural neural systems perform a great deal of information processing via electrochemical pulses. Accordingly, pulse coded neural network concepts are receiving increased attention in artificial neural network research. This increased interest is compounded by continuing advances in the field of VLSI circuit design. This is the first time in history in which it is practical to construct networks of neuron-like circuits of reasonable complexity that can be applied to real problems. We believe that the pioneering work in artificial neural systems presented in this book will lead to further advances that will not only be useful in some practical sense, but may also provide some additional insight into the operation of their natural counterparts.

This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures.

This is the first book to focus on designing run-time reconfigurable systems on FPGAs, in order to gain resource and power efficiency, as well as to improve speed. Case studies in partial reconfiguration guide readers through the FPGA jungle, straight toward a working system. The discussion of partial reconfiguration is comprehensive and practical, with models introduced together with methods to implement efficiently the corresponding systems. Coverage includes concepts for partial module integration and corresponding communication architectures, floorplanning of the on-FPGA resources, physical implementation aspects starting from constraining primitive placement and routing all the way down to the bitstream required to configure the FPGA, and verification of reconfigurable systems.

Analog Circuit Design contains the contribution of 18 tutorials of the 20th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 20 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of:
Topic 1: Low Voltage Low Power, chairman: Andrea Baschirotto
Topic 2: Short Range Wireless Front-Ends, chairman: Arthur van Roermund
Topic 3: Power Management and DC-DC, chairman: Michiel Steyaert.
Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design course.

This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.

Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results.
The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.

This book provides a comprehensive introduction to hardware security, from specification to implementation. Applications discussed include embedded systems ranging from small RFID tags to satellites orbiting the earth. The authors describe a design and synthesis flow, which will transform a given circuit into a secure design incorporating counter-measures against fault attacks. In order to address the conflict between testability and security, the authors describe innovative design-for-testability (DFT) computer-aided design (CAD) tools that support security challenges, engineered for compliance with existing, commercial tools. Secure protocols are discussed, which protect access to necessary test infrastructures and enable the design of secure access controllers.

This book presents state-of-the-art analog and power management IC design techniques for various wireless power transfer (WPT) systems. To create elaborate power management solutions, circuit designers require an in-depth understanding of the characteristics of each converter and regulator in the power chain. This book addresses WPT design issues at both system- and circuit-level, and serves as a handbook offering design insights for research students and engineers in the integrated power electronics area.

Recently there has been increased interest in the development of computer-aided design programs to support the system level designer of integrated circuits more actively. Such design tools hold the promise of raising the level of abstraction at which an integrated circuit is designed, thus releasing the current designers from many of the details of logic and circuit level design. The promise further suggests that a whole new group of designers in neighboring engineering and science disciplines, with far less understanding of integrated circuit design, will also be able to increase their productivity and the functionality of the systems they design. This promise has been made repeatedly as each new higher level of computer-aided design tool is introduced and has repeatedly fallen short of fulfillment. This book presents the results of research aimed at introducing yet higher levels of design tools that will inch the integrated circuit design community closer to the fulfillment of that promise. 1. 1. SYNTHESIS OF INTEGRATED CmCUITS In the integrated circuit (Ie) design process, a behavior that meets certain specifications is conceived for a system, the behavior is used to produce a design in terms of a set of structural logic elements, and these logic elements are mapped onto physical units. The design process is impacted by a set of constraints as well as technological information (i. e. the logic elements and physical units used for the design).

This book provides a survey of the state of the art of technology and future trends in the new family of Smart Power ICs and describes design and applications in a variety of fields ranging from automotive to telecommunications, reliability evaluation and qualification procedures. The book is a valuable source of information and reference for both power IC design specialists and to all those concerned with applications, the development of digital circuits and with system architecture.

"There are three words that characterize this work: thoroughness, completeness and clarity. The authors are congratulated for taking the time to write an excellent linear systems textbook! a ]The authors have used their mastery of the subject to produce a textbook that very effectively presents the theory of linear systems as it has evolved over the last thirty years. The result is a comprehensive, complete and clear exposition that serves as an excellent foundation for more advanced topics in system theory and control." a "IEEE Transactions on Automatic Control

"In assessing the present book as a potential textbook for our first graduate linear systems course, I find...[that] Antsaklis and Michel have contributed an expertly written and high quality textbook to the field and are to be congratulateda ]. Because of its mathematical sophistication and completeness the present book is highly recommended for use, both as a textbook as well as a reference." a "Automatica

Linear systems theory plays a broad and fundamental role in electrical, mechanical, chemical and aerospace engineering, communications, and signal processing. A thorough introduction to systems theory with emphasis on control is presented in this self-contained textbook.

The book examines the fundamental properties that govern the behavior of systems by developing their mathematical descriptions. Linear time-invariant, time-varying, continuous-time, and discrete-time systems are covered. Rigorous development of classic and contemporary topics in linear systems, as well as extensive coverage of stability and polynomial matrix/fractional representation, provide the necessary foundation for further study of systemsand control.

Linear Systems is written as a textbook for a challenging one-semester graduate course; a solutions manual is available to instructors upon adoption of the text. The booka (TM)s flexible coverage and self-contained presentation also make it an excellent reference guide or self-study manual.

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For a treatment of linear systems that focuses primarily on the time-invariant case using streamlined presentation of the material with less formal and more intuitive proofs, see the authorsa (TM) companion book entitled A Linear Systems Primer.

Micro-electronics and so integrated circuit design are heavily driven by technology scaling. The main engine of scaling is an increased system performance at reduced manufacturing cost (per system). In most systems digital circuits dominate with respect to die area and functional complexity. Digital building blocks take full - vantage of reduced device geometries in terms of area, power per functionality, and switching speed. On the other hand, analog circuits rely not on the fast transition speed between a few discrete states but fairly on the actual shape of the trans- tor characteristic. Technology scaling continuously degrades these characteristics with respect to analog performance parameters like output resistance or intrinsic gain. Below the 100 nm technology node the design of analog and mixed-signal circuits becomes perceptibly more dif cult. This is particularly true for low supply voltages near to 1V or below. The result is not only an increased design effort but also a growing power consumption. The area shrinks considerably less than p- dicted by the digital scaling factor. Obviously, both effects are contradictory to the original goal of scaling. However, digital circuits become faster, smaller, and less power hungry. The fast switching transitions reduce the susceptibility to noise, e. g. icker noise in the transistors. There are also a few drawbacks like the generation of power supply noise or the lack of power supply rejection.

Radio-Frequency Microelectronic Circuits for Telecommunication Applications covers the design issues of radio-frequency microelectronic circuits for telecommunication applications with emphasis on devices and circuit-level design. It uses a large number of real examples from industrial design as a vehicle both to teach the principles and to ensure relevance starting from device level modeling to basic RF microelectronic circuit cell design. Modeling for high-frequency operation of both active and passive integrated devices is covered starting from the bipolar transistor to the MOS transistor to the modeling of integrated spiral inductors, resistors, capacitors, varactors and package parasitics structures. A chapter is also devoted to the presentation of the basic definitions and terminology used in RF IC design. The book continues with the presentation of the principal building blocks of an integrated RF front-end, namely, the LNA, the mixer, the VCO and integrated filters. Design paradigms are provided classified on the technology used in each case: pure bipolar, CMOS, BiCMOS or SiGe. Radio-Frequency Microelectronic Circuits for Telecommunication Applications is essential reading for all researchers, practising engineers and designers working in RF electronics. It is also a reference for use in advanced undergraduate or graduate courses in the same field.

This book will describe ultra low-power, integrated circuits and systems designed for the emerging field of neural signal recording and processing, and wireless communication. Since neural interfaces are typically implanted, their operation is highly energy-constrained. This book introduces concepts and theory that allow circuit operation approaching the fundamental limits. Design examples and measurements of real systems are provided. The book will describe circuit designs for all of the critical components of a neural recording system, including: Amplifiers which utilize new techniques to improve the trade-off between good noise performance and low power consumption. Analog and mixed-signal circuits which implement signal processing tasks specific to the neural recording application: Detection of neural spikes Extraction of features that describe the spikes Clustering, a machine learning technique for sorting spikes Weak-inversion operation of analog-domain transistors, allowing processing circuits that reduce the requirements for analog-digital conversion and allow low system-level power consumption. Highly-integrated, sub-mW wireless transmitter designed for the Medical Implant Communications Service (MICS) and ISM bands.

The book is an authoritative collection of contributions by leading experts on the topics of fuzzy logic, multi-valued logic and neural network. Originally written as an homage to Claudio Moraga, seen by his colleagues as an example of concentration, discipline and passion for science, the book also represents a timely reference guide for advance students and researchers in the field of soft computing, and multiple-valued logic.