"Two of the most important trends in sensor development in recent years have been advances in micromachined sensing elements of all kinds, and the increase in intelligence applied at the sensor level. This book addresses both, and provides a good overview of current technology." -- I&CS

Modeling and Simulation of Mixed Analog-Digital Systems brings together in one place important contributions and state-of-the-art research results in this rapidly advancing area. Modeling and Simulation of Mixed Analog-Digital Systems serves as an excellent reference, providing insight into some of the most important issues in the field.

This is the first book on the subject of multi-standard wireless receivers. It covers both the analysis and design aspects of CMOS radio receivers, with primary focus on receivers for mobile terminals. The subject of multi-standard data converter design for base stations is also covered.

Embedded systems are informally defined as a collection of programmable parts surrounded by ASICs and other standard components, that interact continuously with an environment through sensors and actuators. The programmable parts include micro-controllers and Digital Signal Processors (DSPs). Embedded systems are often used in life-critical situations, where reliability and safety are more important criteria than performance. Today, embedded systems are designed with an ad hoc approach that is heavily based on earlier experience with similar products and on manual design. Use of higher-level languages such as C helps structure the design somewhat, but with increasing complexity it is not sufficient. Formal verification and automatic synthesis of implementations are the surest ways to guarantee safety. Thus, the POLIS system which is a co-design environment for embedded systems is based on a formal model of computation. POLIS was initiated in 1988 as a research project at the University of California at Berkeley and, over the years, grew into a full design methodology with a software system supporting it. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach is intended to give a complete overview of the POLIS system including its formal and algorithmic aspects. Hardware-Software Co-Design of Embedded Systems: The POLIS Approach will be of interest to embedded system designers (automotive electronics, consumer electronics and telecommunications), micro-controller designers, CAD developers and students.

After a brief introduction to low-power VLSI design, the design space of ASIP instruction set architectures (ISAs) is introduced with a special focus on important features for digital signal processing. Based on the degrees of freedom offered by this design space, a consistent ASIP design flow is proposed: this design flow starts with a given application and uses incremental optimization of the ASIP hardware, of ASIP coprocessors and of the ASIP software by using a top-down approach and by applying application-specific modifications on all levels of design hierarchy. A broad range of real-world signal processing applications serves as vehicle to illustrate each design decision and provides a hands-on approach to ASIP design. Finally, two complete case studies demonstrate the feasibility and the efficiency of the proposed methodology and quantitatively evaluate the benefits of ASIPs in an industrial context.

This unique book provides an overview of the current state of the art and very recent research results that have been achieved as part of the Low-Power Initiative of the European Union, in the field of analogue, RF and mixed-signal design methodologies and CAD tools.

Uncertainty in key parameters within a chip and between different chips in the deep sub micron area plays a more and more important role. As a result, manufacturing process spreads need to be considered during the design process. Quantitative methodology is needed to ensure faultless functionality, despite existing process variations within given bounds, during product development. This book presents the technological, physical, and mathematical fundamentals for a design paradigm shift, from a deterministic process to a probability-orientated design process for microelectronic circuits. Readers will learn to evaluate the different sources of variations in the design flow in order to establish different design variants, while applying appropriate methods and tools to evaluate and optimize their design.

This book is a step-by-step tutorial on how to design a low-power, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) integrated CMOS analog-to-digital (AD) converter, to respond to the challenge from the rapid growth of IoT. The discussion includes design techniques on both the system level and the circuit block level. In the architecture level, the power-efficient pipelined AD converter, the hybrid AD converter and the time-interleaved AD converter are described. In the circuit block level, the reference voltage buffer, the opamp, the comparator, and the calibration are presented. Readers designing low-power and high-performance AD converters won't want to miss this invaluable reference. Provides an in-depth introduction to the newest design techniques for the power-efficient, high-resolution (not less than 12 bit), and high-speed (not less than 200 MSps) AD converter; Presents three types of power-efficient architectures of the high-resolution and high-speed AD converter; Discusses the relevant circuit blocks (i.e., the reference voltage buffer, the opamp, and the comparator) in two aspects, relaxing the requirements and improving the performance.

This book discusses the building blocks of electronic circuits - the microchips, transistors, resistors, condensers, and so forth, and the boards that support them - from the point of view of mechanics: What are the stresses that result from thermal expansion and contraction? What are the elastic parameters that determine whether a component will survive a certain acceleration? After an introduction to the elements of structural analysis and finite-element analysis, the author turns to components, data and testing. A discussion of leadless chip carriers leads to a detailed thermal analysis of pin grid arrays. For compliant leaded systems, both mechanical (bending and twisting) and thermal stresses are discussed in detail. The book concludes with discussions of the dynamic response of circuit cards, plated holes in cards and boards, and the final assembly of cards and boards.

Since the early-1990s, reducing the dynamic switching power has been the main focus in many of the proposed low-power circuit techniques. At that time, the off-state leakage power was negligible compared to dynamic power. However, as technology scales into the deep-submicron regime, the increase in leakage power can no longer be neglected. Soon, the biggest challenge that SoC designers must resolve is the fact that transistors for digital and memory circuits will be more and more leaky as technology generations advance. The semiconductor industry must therefore reduce leakage current in chip designs by two orders of magnitude over the next ten years, or face an interruption in projected chip complexity. Failure to do so would make the mounting leakage current the big stumbling block to Moore's Law. Furthermore, co-operative approaches between computer-aided design development, circuit design, and technology process must be examined. Multi-threshold voltage CMOS (MTCMOS) technology, that has emerged as an increasingly popular technique to control the escalating leakage power, while maintaining high performance. The book addresses the leakage problem in a number of designs for combinational, sequential, dynamic, and current-steering logic. Moreover, computer-aided design methodologies for designing low-leakage integrated circuits are presented. The book give a survey of state-of-the-art techniques presented in the literature as well as proposed designs that minimize leakage power, while achieving high-performance. Multi-Threshold CMOS Digital Circuits Managing Leakage Power is written for students of VLSI design as well as practicing circuit designers, system designers, CAD tool developers and researchers. It assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit design techniques.

Despite the spectacular breakthroughs of the semiconductor industry, the ability to design integrated circuits under stringent time-to-market requirements is lagging behind integration capacity, so far keeping pace with still valid Moorea (TM)s Law. The resulting gap is threatening with slowing down such a phenomenal growth. The design community believes that it is only by means of powerful CAD tools, design methodologies and even a design paradigm shift, that this design gap can be bridged. In this sense, reuse-based design is seen as a promising solution, and concepts such as IP Block, Virtual Component, and Design Reuse have become commonplace thanks to the significant advances in the digital arena. Unfortunately, the very nature of analog and mixed-signal (AMS) design a "more subtle, hierarchically loose, and handicraft-demandinga" has hindered a similar level of consensus and development.

Aiming at the core of the problem, Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits presents a framework for the reuse-based design of AMS circuits. The framework is founded on three key elements: (1) a CAD-supported hierarchical design flow that facilitates the incorporation of AMS reusable blocks, reduces the overall design time, and expedites the management of increasing AMS design complexity; (2) a complete, clear definition of the AMS reusable block, structured into three separate facets or views: the behavioral, structural, and layout facets, the first two for top-down electrical synthesis and bottom-up verification, the latter used during bottom-up physical synthesis; (3) the design for reusability set of tools, methods, andguidelines that, relying on intensive parameterization as well as on design knowledge capture and encapsulation, allows to produce fully reusable AMS blocks.

Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits features a very detailed, tutorial, and in-depth coverage of all issues and must-have properties of reusable AMS blocks, as well as a thorough description of the methods and tools necessary to implement them. For the first time, this has been done hierarchically, covering one by one the different stages of the design flow, allowing us to examine how the reusable block yields its benefits, both in design time and correct performance.

High-Performance CMOS Continuous-Time Filters is devoted to the design of CMOS continuous-time filters. CMOS is employed because the most complex integrated circuits have been realized with this technology for two decades. The most important advantages and drawbacks of continuous-time filters are clearly shown. The transfer function is one of the most important filter parameters but several others (like intermodulation distortion, power-supply rejection ratio, noise level and dynamic range) are fundamental in the design of high-performance systems. Special attention is paid to the practical aspects of the design, which shows the difference between an academic design and an industrial design. A clear understanding of the behavior of the circuits and techniques is preferred over complex equations or interpretation of simulated results. Step-by-step design procedures are very often used to clarify the use of the techniques and topologies. The organization of this text is hierarchical, starting with the design consideration of the basic building blocks and ending with the design of several high-performance continuous-time filters. Most of the circuits have been fabricated, theoretically analyzed and simulated, and silicon measurement results are compared with each other. High-Performance CMOS Continuous-Time Filters can be used as a text book for senior or graduate courses on this topic and can also be useful for industrial engineers as a reference book.

Standard voltages used in today's ICs may vary from about 1.3V to more than 100V, depending on the technology and the application. High voltage is therefore a relative notion. High Voltage Devices and Circuits in Standard CMOS Technologies is mainly focused on standard CMOS technologies, where high voltage (HV) is defined as any voltage higher than the nominal (low) voltage, i.e. 5V, 3.3V, or even lower. In this standard CMOS environment, IC designers are more and more frequently confronted with HV problems, particularly at the I/O level of the circuit. In the first group of applications, a large range of industrial or consumer circuits either require HV driving capabilities, or are supposed to work in a high-voltage environment. This includes ultrasonic drivers, flat panel displays, robotics, automotive, etc. On the other hand, in the emerging field of integrated microsystems, MEMS actuators mainly make use of electrostatic forces involving voltages in the typical range of 30 to 60V. Last but not least, with the advent of deep sub-micron and/or low-power technologies, the operating voltage tends towards levels ranging from 1V to 2.5V, while the interface needs to be compatible with higher voltages, such as 5V. For all these categories of applications, it is usually preferable to perform most of the signal processing at low voltage, while the resulting output rises to a higher voltage level. Solving this problem requires some special actions at three levels: technology, circuit design and layout. High Voltage Devices and Circuits in Standard CMOS Technologies addresses these topics in a clear and organized way. The theoretical background is supported by practical information and designexamples. It is an invaluable reference for researchers and professionals in both the design and device communities.

This book offers readers a clear guide to implementing engineering applications with FPGAs, from the mathematical description to the hardware synthesis, including discussion of VHDL programming and co-simulation issues. Coverage includes FPGA realizations such as: chaos generators that are described from their mathematical models; artificial neural networks (ANNs) to predict chaotic time series, for which a discussion of different ANN topologies is included, with different learning techniques and activation functions; random number generators (RNGs) that are realized using different chaos generators, and discussions of their maximum Lyapunov exponent values and entropies. Finally, optimized chaotic oscillators are synchronized and realized to implement a secure communication system that processes black and white and grey-scale images. In each application, readers will find VHDL programming guidelines and computer arithmetic issues, along with co-simulation examples with Active-HDL and Simulink.The whole book provides a practical guide to implementing a variety of engineering applications from VHDL programming and co-simulation issues, to FPGA realizations of chaos generators, ANNs for chaotic time-series prediction, RNGs and chaotic secure communications for image transmission.

Thoroughly revised and updated, this highly successful textbook guides students through the analysis and design of transistor circuits. It covers a wide range of circuitry, both linear and switching.
Transistor Circuit Techniques: Discrete and Integrated provides students with an overview of fundamental qualitative circuit operation, followed by an examination of analysis and design procedure. It incorporates worked problems and design examples to illustrate the concepts. This third edition includes two additional chapters on power amplifiers and power supplies, which further develop many of the circuit design techniques introduced in earlier chapters.
Part of the Tutorial Guides in Electronic Engineering series, this book is intended for first and second year undergraduate courses. A complete text on its own, it offers the added advantage of being cross-referenced to other titles in the series. It is an ideal textbook for both students and instructors.

This book primarily focuses on the radiation effects and compact model of silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs). It introduces the small-signal equivalent circuit of SiGe HBTs including the distributed effects, and proposes a novel direct analytical extraction technique based on non-linear rational function fitting. It also presents the total dose effects irradiated by gamma rays and heavy ions, as well as the single-event transient induced by pulse laser microbeams. It offers readers essential information on the irradiation effects technique and the SiGe HBTs model using that technique.

This book brings together a selection of the best papers from the sixteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in September 2013 in Paris, France. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems and mixed-technology systems.

This volume contains the proceedings of a workshop on Analog Integrated Neural Systems held May 8, 1989, in connection with the International Symposium on Circuits and Systems. The presentations were chosen to encompass the entire range of topics currently under study in this exciting new discipline. Stringent acceptance requirements were placed on contributions: (1) each description was required to include detailed characterization of a working chip, and (2) each design was not to have been published previously. In several cases, the status of the project was not known until a few weeks before the meeting date. As a result, some of the most recent innovative work in the field was presented. Because this discipline is evolving rapidly, each project is very much a work in progress. Authors were asked to devote considerable attention to the shortcomings of their designs, as well as to the notable successes they achieved. In this way, other workers can now avoid stumbling into the same traps, and evolution can proceed more rapidly (and less painfully). The chapters in this volume are presented in the same order as the corresponding presentations at the workshop. The first two chapters are concerned with fmding solutions to complex optimization problems under a predefmed set of constraints. The first chapter reports what is, to the best of our knowledge, the first neural-chip design. In each case, the physics of the underlying electronic medium is used to represent a cost function in a natural way, using only nearest-neighbor connectivity.

This book presents a thorough state-of-the-art review for internally compensated Low Dropout Regulators (IC-LDO). It serves as a useful guide for circuit designers. The advantages and disadvantages of each cell proposed are highlighted. The authors describe an alternative to the classical topology; the Flipped Voltage Follower (FVF), which has been recently applied in the design of internally compensated LDOs to enhance their performances. This book provides novel circuits enhancing those parameters of LDO related with frequency behavior and power consumption. These solutions, as well as their appropriate design methodology, are properly described within the text.

Updated to integrated modular avionics, and cabin and aircraft information systems Ideal for students gaining EASA Part 66 licences, particularly the B1 or B2 licence One of Routledge's core aircraft maintenance titles.

Hardware Software Co-Design of a Multimedia SOC Platform is one of the first of its kinds to provide a comprehensive overview of the design and implementation of the hardware and software of an SoC platform for multimedia applications. Topics covered in this book range from system level design methodology, multimedia algorithm implementation, a sub-word parallel, single-instruction-multiple data (SIMD) processor design, and its virtual platform implementation, to the development of an SIMD parallel compiler as well as a real-time operating system (RTOS). Hardware Software Co-Design of a Multimedia SOC Platform is written for practitioner engineers and technical managers who want to gain first hand knowledge about the hardware-software design process of an SoC platform. It offers both tutorial-like details to help readers become familiar with a diverse range of subjects, and in-depth analysis for advanced readers to pursue further.

For over three decades now, silicon capacity has steadily been doubling every year and a half with equally staggering improvements continuously being observed in operating speeds. This increase in capacity has allowed for more complex systems to be built on a single silicon chip. Coupled with this functionality increase, speed improvements have fueled tremendous advancements in computing and have enabled new multi-media applications. Such trends, aimed at integrating higher levels of circuit functionality are tightly related to an emphasis on compactness in consumer electronic products and a widespread growth and interest in wireless communications and products. These trends are expected to persist for some time as technology and design methodologies continue to evolve and the era of Systems on a Chip has definitely come of age. While technology improvements and spiraling silicon capacity allow designers to pack more functions onto a single piece of silicon, they also highlight a pressing challenge for system designers to keep up with such amazing complexity. To handle higher operating speeds and the constraints of portability and connectivity, new circuit techniques have appeared. Intensive research and progress in EDA tools, design methodologies and techniques is required to empower designers with the ability to make efficient use of the potential offered by this increasing silicon capacity and complexity and to enable them to design, test, verify and build such systems.

The move to higher levels of integration has increased the fraction of application-specific integrated circuit (ASIC) designs containing both analog and digital circuits. While the die area for the analog portion of these chips is modest, the design time is often significant. This has motivated the development of automated analog physical design tools for cell-level place-and-route and system-level signal-integrity-routing. To date, there is no tool that has specifically addressed the critical design task of synthesizing the power distribution for the analog portion of an analog or mixed-signal ASIC. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs describes algorithms for analog power distribution synthesis and demonstrates their effectiveness. Existing digital power bus synthesis algorithms have failed to address critical concerns for analog circuitry, thus yielding unacceptable results. These tools synthesize only the bus component of power distribution networks and only consider simplified DC aspects of macros and busses. Readers of the companion book in this series, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits (Kluwer Academic Publishers), already recognize the inadequacy of this simplified view of the noise and power distribution problem in mixed-signal integrated circuits. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs addresses power distribution synthesis for mixed-signal integrated circuits. Several key challenges in power distribution design are identified and automated methods to overcome them are described. This book presents a new formulation for the analog powerdistribution synthesis problem which synthesizes both the power busses power I/O cell assignment by evaluating DC, AC, and transient interaction between the macros, busses, chip substrate, and package. Furthermore, algorithms are introduced which simultaneously optimize power I/O cell assignment, macro cell substrate coupling, power bus topology selection and power bus sizing. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs will be of interest to CAD designers and researchers specializing in physical design, modelling and circuit synthesis.

The objective of this book is to advance the current knowledge of sensor research particularly highlighting recent advances, current work, and future needs. The goal is to share current technologies and steer future efforts in directions that will benefit the majority of researchers and practitioners working in this broad field of study.

Bridges the gap between electromagnetics and circuits by addressing electrometric modeling (EM) using the Partial Element Equivalent Circuit (PEEC) method This book provides intuitive solutions to electromagnetic problems by using the Partial Element Equivalent Circuit (PEEC) method. This book begins with an introduction to circuit analysis techniques, laws, and frequency and time domain analyses. The authors also treat Maxwell's equations, capacitance computations, and inductance computations through the lens of the PEEC method. Next, readers learn to build PEEC models in various forms: equivalent circuit models, non-orthogonal PEEC models, skin-effect models, PEEC models for dielectrics, incident and radiate field models, and scattering PEEC models. The book concludes by considering issues like stability and passivity, and includes five appendices some with formulas for partial elements. * Leads readers to the solution of a multitude of practical problems in the areas of signal and power integrity and electromagnetic interference * Contains fundamentals, applications, and examples of the PEEC method * Includes detailed mathematical derivations Circuit Oriented Electromagnetic Modeling Using the PEEC Techniques is a reference for students, researchers, and developers who work on the physical layer modeling of IC interconnects and Packaging, PCBs, and high speed links.