This "must have" reference work for semiconductor professionals and researchers provides a basic understanding of how the most commonly used tools and techniques in silicon-based semiconductors are applied to understanding the root cause of electrical failures in integrated circuits.

"System level testing is becoming increasingly important. It is driven by the incessant march of complexity ... which is forcing us to renew our thinking on the processes and procedures that we apply to test and diagnosis of systems. In fact, the complexity defines the system itself which, for our purposes, is Aany aggregation of related elements that together form an entity of sufficient complexity for which it is impractical to treat all of the elements at the lowest level of detail . System approaches embody the partitioning of problems into smaller inter-related subsystems that will be solved together. Thus, words like hierarchical, dependence, inference, model, and partitioning are frequent throughout this text. Each of the authors deals with the complexity issue in a similar fashion, but the real value in a collected work such as this is in the subtle differences that may lead to synthesized approaches that allow even more progress. The works included in this volume are an outgrowth of the 2nd International Workshop on System Test and Diagnosis held in Alexandria, Virginia in April 1998. The first such workshop was held in Freiburg, Germany, six years earlier. In the current workshop nearly 50 experts from around the world struggled over issues concerning the subject... In this volume, a select group of workshop participants was invited to provide a chapter that expanded their workshop presentations and incorporated their workshop interactions... While we have attempted to present the work as one volume and requested some revision to the work, the content of the individual chapters was not edited significantly. Consequently, you will see different approaches to solving the sameproblems and occasional disagreement between authors as to definitions or the importance of factors. ... The works collected in this volume represent the state-of-the-art in system test and diagnosis, and the authors are at the leading edge of that science...." From the Preface

Integrated circuit technology is widely used for the full integration of electronic systems. In general, these systems are realized using digital techniques implemented in CMOS technology. The low power dissipation, high packing density, high noise immunity, ease of design and the relative ease of scaling are the driving forces of CMOS technology for digital applications. Parts of these systems cannot be implemented in the digital domain and will remain analog. In order to achieve complete system integration these analog functions are preferably integrated in the same CMOS technology. An important class of analog circuits that need to be integrated in CMOS are analog filters. This book deals with very high frequency (VHF) filters, which are filters with cut-off frequencies ranging from the low megahertz range to several hundreds of megahertz. Until recently the maximal cut-off frequencies of CMOS filters were limited to the low megahertz range. By applying the techniques presented in this book the limit could be pushed into the true VHF domain, and integrated VHF filters become feasible. Application of these VHF filters can be found in the field of communication, instrumentation and control systems. For example, pre and post filtering for high-speed AD and DA converters, signal reconstruction, signal decoding, etc. The general design philosophy used in this book is to allow only the absolute minimum of signal carrying nodes throughout the whole filter. This strategy starts at the filter synthesis level and is extended to the level of electronic circuitry. The result is a filter realization in which all capacitators (including parasitics) have a desired function. The advantage of this technique is that high frequency parasitic effects (parasitic poles/zeros) are minimally present. The book is a reference for engineers in research or development, and is suitable for use as a text for advanced courses on the subject. >

The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work.

Are memory applications more critical than they have been in the past? Yes, but even more critical is the number of designs and the sheer number of bits on each design. It is assured that catastrophes, which were avoided in the past because memories were small, will easily occur if the design and test engineers do not do their jobs very carefully.
High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is based on the author's 20 years of experience in memory design, memory reliability development and memory self test.

High Performance Memory Testing: Design Principles, Fault Modeling and Self Test is written for the professional and the researcher to help them understand the memories that are being tested.

Oversampled A/D converters have become very popular in recent years. Some of their advantages include relaxed requirements for anti-alias filters, relaxed requirements for component matching, high resolution and compatibility with digital VLSI technology. There is a significant amount of literature discussing the principle, theory and implementation of various oversampled converters. Such converters are likely to continue to proliferate in the foreseeable future. Additionally, more recently there has been great interest in low voltage and low power circuit design. New design techniques have been proposed for both the digital domain and the analog domain. Both trends point to the importance of the low-power design of oversampled A/D converters. Unfortunately, there has been no systematic study of the optimal design of modulators for oversampled converters. Design has generally focused on new architectures with little attention being paid to optimization. The goal of Design of Modulators for Oversampled Converters is to develop a methodology for the optimal design of modulators in oversampled converters. The primary focus of the presentation is on minimizing power consumption and understanding and limiting the nonlinearities that result in such converters. Design of Modulators for Oversampled Converters offers a quantitative justification for the various design tradeoffs and serves as a guide for designing low-power highly linear oversampled converters. Design of Modulators for Oversampled Converters will serve as a valuable guide for circuit design practitioners, university researchers and graduate students who are interested in this fast-moving area.

The seventh book in the CHDL Series is composed of a selection of the best articles from the Forum on Specification and Design Languages (FDL'04). FDL is the European Forum to learn and exchange on new trends on the application of languages and models for the design of electronic and heterogeneous systems.

The forum was structured around four workshops that are all represented in the book by outstanding articles: Analog and Mixed-Signal Systems, UML-based System Specification and Design, C/C++-Based System Design and Languages for Formal Specification and Verification.

The Analog and Mixed-Signal Systems contributions bring some answers to the difficult problem of co-simulating discrete and continuous models of computation. The UML-based System Specification and Design chapters bring insight into how to use the Model Driven Engineering to design Systems-on-Chip. The C/C++-Based System Design articles mainly explore system level design with SystemC. The Languages for Formal
Specification and Verification is represented by an invited contribution on the use of temporal assertions for symbolic model checking and simulation. And finally chapter in this book contributed by preeminent members of the automotive design industry presents the recent industry standard AutoSAR.

Overall Advances in Design and Specification Languages for SoCs is an excellent opportunity to catch up with the latest research developments in the field of languages for electronic and heterogeneous system design.

System-on-Chip for Real-Time Applications will be of interest to engineers, both in industry and academia, working in the area of SoC VLSI design and application. It will also be useful to graduate and undergraduate students in electrical and computer engineering and computer science.
A selected set of papers from the 2nd International Workshop on Real-Time Applications were used to form the basis of this book. It is organized into the following chapters:

-Introduction;
-Design Reuse;
-Modeling;
-Architecture;
-Design Techniques;
-Memory;
-Circuits;
-Low Power;
-Interconnect and Technology;
-MEMS.System-on-Chip for Real-Time Applications contains many signal processing applications and will be of particular interest to those working in that community.

Integrated circuit densities and operating speeds continue to rise at an exponential rate. Chips, however, cannot get larger and faster without a sharp decrease in power consumption beyond the current levels. Minimization of power consumption in VLSI chips has thus become an important design objective. In fact, with the explosive growth in demand for portable electronics and the usual push toward more complex functionality and higher performance, power consumption has in many cases become the limiting factor in satisfying the market demand. A new generation of power-conscious CAD tools are coming onto the market to help designers estimate, optimize and verify power consumption levels at most stages of the IC design process. These tools are especially prevalent at the register-transfer level and below. There is a great need for similar tools and capabilities at the behavioral and system levels of the design process. Many researchers and CAD tool developers are working on high-level power modeling and estimation, as well as power-constrained high-level synthesis and optimization. Techniques and tools alone are, however, insufficient to optimize VLSI circuit power dissipation - a consistent and convergent design methodology is also required. Power Optimization and Synthesis at Behavioral and System Levels Using Formal Methods was written to address some of the key problems in power analysis and optimization early in the design process. In particular, this book focuses on power macro-modeling based on regression analysis and power minimization through behavioral transformations, scheduling, resource assignment and hardware/software partitioning and mapping. What differentiates this book from other published work on the subject is the mathematical basis and formalism behind the algorithms and the optimality of these algorithms subject to the stated assumptions. From the Foreword: This book makes an important contribution to the field of system design technologies by presenting a set of algorithms with guaranteed optimality properties, that can be readily applied to system-level design. This contribution is timely, because it fills the need of new methods for a new design tool generation, which supports the design of electronic systems with even more demanding requirements'. Giovanni De Micheli, Professor, Stanford University

Particle simulation of semiconductor devices is a rather new field which has started to catch the interest of the world's scientific community. It represents a time-continuous solution of Boltzmann's transport equation, or its quantum mechanical equivalent, and the field equation, without encountering the usual numerical problems associated with the direct solution. The technique is based on first physical principles by following in detail the transport histories of indi vidual particles and gives a profound insight into the physics of semiconductor devices. The method can be applied to devices of any geometrical complexity and material composition. It yields an accurate description of the device, which is not limited by the assumptions made behind the alternative drift diffusion and hydrodynamic models, which represent approximate solutions to the transport equation. While the development of the particle modelling technique has been hampered in the past by the cost of computer time, today this should not be held against using a method which gives a profound physical insight into individual devices and can be used to predict the properties of devices not yet manufactured. Employed in this way it can save the developer much time and large sums of money, both important considerations for the laboratory which wants to keep abreast of the field of device research. Applying it to al ready existing electronic components may lead to novel ideas for their improvement. The Monte Carlo particle simulation technique is applicable to microelectronic components of any arbitrary shape and complexity.

Synchronization of chaotic systems, a patently nonlinear phenomenon, has emerged as a highly active interdisciplinary research topic at the interface of physics, biology, applied mathematics and engineering sciences. In this connection, time-delay systems described by delay differential equations have developed as particularly
suitable tools for modeling specific dynamical systems. Indeed, time-delay is ubiquitous in many physical systems, for example due to finite
switching speeds of amplifiers in electronic circuits, finite lengths of vehicles in traffic flows, finite signal propagation times in biological networks and circuits, and quite generally whenever memory effects are relevant.
This monograph presents the basics of chaotic time-delay systems and their synchronization with an emphasis on the effects of time-delay feedback which give rise to new collective dynamics.
Special attention is devoted to scalar chaotic/hyperchaotic time-delay
systems, and some higher order models, occurring in different branches of science and technology as well as to the synchronization of their coupled versions.

Last but not least, the presentation as a whole strives for a balance between the necessary mathematical description of the basics
and the detailed presentation of real-world applications.

Analog Circuit Design contains the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 17 in this successful series of Analog Circuit Design.

This book collects the latest theoretical and technological concepts in the design and control of various linear machines and drive systems. Discussing advances in the new linear machine topologies, integrated modeling, multi-objective optimization techniques, and high-performance control strategies, it focuses on emerging applications of linear machines in transportation and energy systems. The book presents both theoretical and practical/experimental results, providing a consistent compilation of fundamental theories, a compendium of current research and development activities as well as new directions to overcome critical limitations.

This book presents innovative solutions for the implementation of Sigma-Delta Modulation (SDM) based Analog-to-Digital Conversion (ADC), required for the next generation of wireless hand-held terminals. These devices will be based on the so-called "multi-standard transceiver chipsets, " integrated in nanometer CMOS technologies. One of the most challenging and critical parts in such transceivers is the analog-digital interface, because of the assorted signal bandwidths and dynamic ranges that can be required to handle the A/D conversion for several operation modes.

This book describes new adaptive and reconfigurable SDM ADC topologies, circuit strategies and synthesis methods, specially suited for multi-standard wireless telecom systems and future Software-defined-radios (SDRs) integrated in nanoscale CMOS. It is a practical book, going from basic concepts to the frontiers of SDM architectures and circuit implementations, which are explained in a didactical and systematic way. It gives a comprehensive overview of the state-of-the-art performance, challenges and practical solutions, providing the necessary insight to implement successful design, through an efficient design and synthesis methodology. Readers will learn a number of practical skills - from system-level design to experimental measurements and testing."

I am very pleased to play even a small part in the publication of this book on the SIGNAL language and its environment POLYCHRONY. I am sure it will be a s- ni?cant milestone in the development of the SIGNAL language, of synchronous computing in general, and of the data?ow approach to computation. In data?ow, the computation takes place in a producer-consumer network of - dependent processing stations. Data travels in streams and is transformed as these streams pass through the processing stations (often called ?lters). Data?ow is an attractive model for many reasons, not least because it corresponds to the way p- duction, transportation, andcommunicationare typicallyorganizedin the real world (outside cyberspace). I myself stumbled into data?ow almost against my will. In the mid-1970s, Ed Ashcroft and I set out to design a "super" structured programming language that, we hoped, would radically simplify proving assertions about programs. In the end, we decided that it had to be declarative. However, we also were determined that iterative algorithms could be expressed directly, without circumlocutions such as the use of a tail-recursive function. The language that resulted, which we named LUCID, was much less traditional then we would have liked. LUCID statements are equations in a kind of executable temporallogic thatspecifythe (time)sequencesof variablesinvolvedin aniteration.

This book provides readers with an overview of the design, fabrication, simulation, and reliability of nanoscale semiconductor devices, MEMS, and sensors, as they serve for realizing the next-generation internet of things. The authors focus on how the nanoscale structures interact with the electrical and/or optical performance, how to find optimal solutions to achieve the best outcome, how these apparatus can be designed via models and simulations, how to improve reliability, and what are the possible challenges and roadblocks moving forward.

In Security Trends for FPGA's the authors present an analysis of current threats against embedded systems and especially FPGAs. They discuss about requirements according to the FIPS standard in order to build a secure system. This point is of paramount importance as it guarantees the level of security of a system. Also highlighted are current vulnerabilities of FPGAs at all the levels of the security pyramid. It is essential from a design point of view to be aware of all the levels in order to provide a comprehensive solution. The strength of a system is defined by its weakest point; there is no reason to enhance other protection means, if the weakest point remains untreated. Many severe attacks have considered this weakness in order not to face brute force attack complexity. Several solutions are proposed in Security Trends for FPGA's especially at the logical, architecture and system levels in order to provide a global solution.

Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become one of the most popular implementation media for digital circuits and have grown into a $2 billion per year industry. As process geometries have shrunk into the deep-submicron region, the logic capacity of FPGAs has greatly increased, making FPGAs a viable implementation alternative for larger and larger designs. To make the best use of these new deep-submicron processes, one must re-design one's FPGAs and Computer- Aided Design (CAD) tools. Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes. Three factors combine to determine the performance of an FPGA: the quality of the CAD tools used to map circuits into the FPGA, the quality of the FPGA architecture, and the electrical (i.e. transistor-level) design of the FPGA. Architecture and CAD for Deep-Submicron FPGAs examines all three of these issues in concert. In order to investigate the quality of different FPGA architectures, one needs CAD tools capable of automatically implementing circuits in each FPGA architecture of interest. Once a circuit has been implemented in an FPGA architecture, one next needs accurate area and delay models to evaluate the quality (speed achieved, area required) of the circuit implementation in the FPGA architecture under test. This book therefore has three major foci: the development of a high-quality and highly flexible CAD infrastructure, the creation of accurate area and delay models for FPGAs, and the study of several important FPGA architectural issues. Architecture and CAD for Deep-Submicron FPGAs is an essential reference for researchers, professionals and students interested in FPGAs.

This book contains a selection of papers presented at the 16th AISEM ( Associazione Italiana Sensori e Microsistemi ) National Conference on Sensors and Microsystems, held in Rome 7-9 February 2011. The conference highlighted updated results from both theoretical and applied research in the field of sensors and microsystems. This book presents material in an interdisciplinary approach, covering many aspects of the disciplines related to sensors and microsystems, including physics, chemistry, materials science, biology and applications.

This book provides students and practicing chip designers with an easy-to-follow yet thorough, introductory treatment of the most promising emerging memories under development in the industry. Focusing on the chip designer rather than the end user, this book offers expanded, up-to-date coverage of emerging memories circuit design. After an introduction on the old solid-state memories and the fundamental limitations soon to be encountered, the working principle and main technology issues of each of the considered technologies (PCRAM, MRAM, FeRAM, ReRAM) are reviewed and a range of topics related to design is explored: the array organization, sensing and writing circuitry, programming algorithms and error correction techniques are reviewed comparing the approach followed and the constraints for each of the technologies considered. Finally the issue of radiation effects on memory devices has been briefly treated. Additionally some considerations are entertained about how emerging memories can find a place in the new memory paradigm required by future electronic systems. This book is an up-to-date and comprehensive introduction for students in courses on memory circuit design or advanced digital courses in VLSI or CMOS circuit design. It also serves as an essential, one-stop resource for academics, researchers and practicing engineers.

This comprehensive treatment of the challenges in low-power RF CMOS design deals with the design and implementation of low- power wireless transceivers in a standard digital CMOS process. It addresses trade-offs and techniques that improve performance, from the component level to the architectural level.

Mechanical stress affects the magnitude of base-emitter voltages of forward biased bipolar transistors. This phenomenon is called the piezojunction effect. The piezojunction effect is the main cause of inaccuracy and drift in integrated temperature sensors and bandgap voltage references. The aim of The Piezojunction Effect in Silicon Integrated Circuits and Sensors is twofold. Firstly, to describe techniques that can reduce the mechanical-stress-induced inaccuracy and long-term instability. Secondly, to show, that the piezojunction effect can be applied for new types of mechanical-sensor structures. During IC fabrication and packaging thermo-mechanical stress is induced, when the packaged chips cool down to the temperature of application. The piezojunction effect is caused by a stress-induced change in the conductivity of the minority-charge carriers, while the piezoresistive effect is caused by a similar effect for the majority-charge carriers. To characterise the anisotropic piezojunction effect, the authors performed systematic investigations over wide ranges of mechanical stress and temperature. The experiments have been performed for various crystal and stress orientations. The experimental results have been used to extract the first- and second-order piezojunction (FOPJ and SOPJ) coefficients for bipolar transistors. It is shown how the knowledge of the piezojunction and piezoresistive coefficients can used to minimize the undesirable mechanical-stress effects on the electrical characteristics of transistors and resistors, respectively. Devices with lower mechanical-stress sensitivity can be found by comparing their piezo-coefficients. The layout of the device can also be optimized to reduce the mechanical-stress sensitivity. As a next step it is shown, how the knowledge of the piezo-effects on device level can be used to predict and to reduce their negative influence on circuit level. This is demonstrated for a number of important basic circuits, including translinear circuits, temperature transducers and bandgap references. Finally, it is shown how the piezojunction effect can be used to fabricate stress-sensing elements. It appears that, in comparison with resistive stress-sensing elements, the piezojunction sensors have the advantage of a smaller size and very low power dissipation.

This book investigates the susceptibility of intrinsic physically unclonable function (PUF) implementations on reconfigurable hardware to optical semi-invasive attacks from the chip backside. It explores different classes of optical attacks, particularly photonic emission analysis, laser fault injection, and optical contactless probing. By applying these techniques, the book demonstrates that the secrets generated by a PUF can be predicted, manipulated or directly probed without affecting the behavior of the PUF. It subsequently discusses the cost and feasibility of launching such attacks against the very latest hardware technologies in a real scenario. The author discusses why PUFs are not tamper-evident in their current configuration, and therefore, PUFs alone cannot raise the security level of key storage. The author then reviews the potential and already implemented countermeasures, which can remedy PUFs' security-related shortcomings and make them resistant to optical side-channel and optical fault attacks. Lastly, by making selected modifications to the functionality of an existing PUF architecture, the book presents a prototype tamper-evident sensor for detecting optical contactless probing attempts.

Microprocessors increasingly control and monitor our most critical systems, including automobiles, airliners, medical systems, transportation grids, and defense systems. The relentless march of semiconductor process technology has given engineers exponentially increasing transistor budgets at constant recurring cost. This has encouraged increased functional integration onto a single die, as well as increased architectural sophistication of the functional units themselves. Additionally, design cycle times are decreasing, thus putting increased schedule pressure on engineers. Not surprisingly, this environment has led to a number of uncaught design flaws. Traditional simulation-based design verification has not kept up with the scale or pace of modern microprocessor system design. Formal verification methods offer the promise of improved bug-finding capability, as well as the ability to establish functional correctness of a detailed design relative to a high-level specification. However, widespread use of formal methods has had to await breakthroughs in automated reasoning, integration with engineering design languages and processes, scalability, and usability.

This book presents several breakthrough design and verification techniques that allow these powerful formal methods to be employed in the real world of high-assurance microprocessor system design.

This book serves as a reference for researchers and designers in Embedded Systems who need to explore design alternatives. It provides a design space exploration methodology for the analysis of system characteristics and the selection of the most appropriate architectural solution to satisfy requirements in terms of performance, power consumption, number of required resources, etc. Coverage focuses on the design of complex multimedia applications, where the choice of the optimal design alternative in terms of application/architecture pair is too complex to be pursued through a full search comparison, especially because of the multi-objective nature of the designer 's goal, the simulation time required and the number of parameters of the multi-core architecture to be optimized concurrently.