This book presents novel algorithms for designing Discrete-Time Sliding Mode Controllers (DSMCs) for Networked Control Systems (NCSs) with both types of fractional delays namely deterministic delay and random delay along with different packet loss conditions such as single packet loss and multiple packet loss that occur within the sampling period. Firstly, the switching type and non-switching type algorithms developed for the deterministic type fractional delay where the delay is compensated using Thiran's approximation technique. A modified discrete-time sliding surface is proposed to derive the discrete-time sliding mode control algorithms. The algorithm is further extended for the random fractional delay with single packet loss and multiple packet loss situations. The random fractional delay is modelled using Poisson's distribution function and packet loss is modelled by means of Bernoulli's function. The condition for closed loop stability in all above situations are derived using the Lyapunov function. Lastly, the efficacy of the proposed DSMC algorithms are demonstrated by extensive simulations and also experimentally validated on a servo system.

CMOS Test and Evaluation: A Physical Perspective is a single source for an integrated view of test and data analysis methodology for CMOS products, covering circuit sensitivities to MOSFET characteristics, impact of silicon technology process variability, applications of embedded test structures and sensors, product yield, and reliability over the lifetime of the product. This book also covers statistical data analysis and visualization techniques, test equipment and CMOS product specifications, and examines product behavior over its full voltage, temperature and frequency range.

This book arises from experience the authors have gained from years of work as industry practitioners in the field of Electronic System Level design (ESL). At the heart of all things related to Electronic Design Automation (EDA), the core issue is one of models: what are the models used for, what should the models contain, and how should they be written and distributed. Issues such as interoperability and tool transportability become central factors that may decide which ones are successful and those that cannot get sufficient traction in the industry to survive.

Through a set of real examples taken from recent industry experience, this book will distill the state of the art in terms of System-Level Design models and provide practical guidance to readers that can be put into use. This book is an invaluable tool that will aid readers in their own designs, reduce risk in development projects, expand the scope of design projects, and improve developmental processes and project planning.

The main focus of this book is to provide the reader with a deep understanding of modeling and design strategies of Current-Mode digital circuits, as well as to organize in a coherent manner all the original and powerful authorsa (TM) results in the domain of Current-Mode digital circuits.

Model and Design of Bipolar and MOS Current-Mode Logic includes bipolar Current-Mode digital circuits, which emerged as an approach to realize digital circuits with the highest speed, and CMOS Current-Mode digital circuits, which together with its speed performance has been rediscovered to allow logic gates implementations having the feature of low noise level generation.

Model and Design of Bipolar and MOS Current-Mode Logic allows the reader not only to understand the operating principle and the features of bipolar and MOS Current-Mode digital circuits, but also to design optimized digital gates. And, although the material is presented in a formal and theoretical manner, much emphasis is devoted to a design perspective. Moreover, to further link the booka (TM)s theoretical aspects with practical issues, and to provide the reader with an idea of the real order of magnitude involved assuming actual technologies, numerical examples together with SPICE simulations are included in the book.

Model and Design of Bipolar and MOS Current-Mode Logic can be used as a reference to practicing engineers working in this area and as text book to senior undergraduate, graduate and postgraduate students (already familiar with electronic circuits and logic gates) who want to extend their knowledge and cover all aspects of the analysis and design of Current-Mode digital circuits.

This book shows readers how to design semiconductor devices using the most common and lowest cost logic CMOS processes. Readers will benefit from the author's extensive, industrial experience and the practical approach he describes for designing efficiently semiconductor devices that typically have to be implemented using specialized processes that are expensive, time-consuming, and low-yield. The author presents an integrated picture of semiconductor device physics and manufacturing techniques, as well as numerous practical examples of device designs that are tried and true.

This book reveals why carbon is playing such an increasingly prominent role as a sensing material. The various steps that transform a raw material in a sensing device are thoroughly presented and critically discussed.The authors deal with all aspects of carbon-based sensors, starting from the various hybridization and allotropes of carbon, with specific focus on micro and nano sized carbons (e.g., carbon nanotubes, graphene) and their growth processes. The discussion then moves to the role of functionalization and the different routes to achieve it. Finally, a number of sensing applications in various fields are presented, highlighting the connection with the basic properties of the various carbon allotropes. Readers will benefit from this book s bottom-up approach, which starts from the local bonding in carbon solids and ends with sensing applications, linking the local hybridization of carbon atoms and its modification by functionalization to specific device performance. This book is a must-have in the library of any scientist involved in carbon based sensing application."

This book considers the design and development of nanoelectronic computing circuits, systems and architectures focusing particularly on memristors, which represent one of today's latest technology breakthroughs in nanoelectronics. The book studies, explores, and addresses the related challenges and proposes solutions for the smooth transition from conventional circuit technologies to emerging computing memristive nanotechnologies. Its content spans from fundamental device modeling to emerging storage system architectures and novel circuit design methodologies, targeting advanced non-conventional analog/digital massively parallel computational structures. Several new results on memristor modeling, memristive interconnections, logic circuit design, memory circuit architectures, computer arithmetic systems, simulation software tools, and applications of memristors in computing are presented. High-density memristive data storage combined with memristive circuit-design paradigms and computational tools applied to solve NP-hard artificial intelligence problems, as well as memristive arithmetic-logic units, certainly pave the way for a very promising memristive era in future electronic systems. Furthermore, these graph-based NP-hard problems are solved on memristive networks, and coupled with Cellular Automata (CA)-inspired computational schemes that enable computation within memory. All chapters are written in an accessible manner and are lavishly illustrated. The book constitutes an informative cornerstone for young scientists and a comprehensive reference to the experienced reader, hoping to stimulate further research on memristive devices, circuits, and systems.

Introduction The exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as inter connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti mization problems emerging with the advent of very deep submicron technologies in semiconductor processing. We hope that it will stimulate more people to perform research that leads to advances in the design and development of more efficient, effective, and elegant algorithms and design tools. Organization of the Book The book is organized as follows. A multi-stage simulated annealing algorithm that integrates floorplanning and interconnect planning is pre sented in Chapter 1. To reduce the run time, different interconnect plan ning approaches are applied in different ranges of temperatures. Chapter 2 introduces a new design methodology - the interconnect-centric design methodology and its centerpiece, interconnect planning, which consists of physical hierarchy generation, floorplanning with interconnect planning, and interconnect architecture planning. Chapter 3 investigates a net-cut minimization based placement tool, Dragon, which integrates the state of the art partitioning and placement techniques."

This book discusses the opportunities offered by disruptive technologies to overcome the economical and physical limits currently faced by the electronics industry. It provides a new methodology for the fast evaluation of an emerging technology from an architectural prospective and discusses the implications from simple circuits to complex architectures. Several technologies are discussed, ranging from 3-D integration of devices (Phase Change Memories, Monolithic 3-D, Vertical NanoWires-based transistors) to dense 2-D arrangements (Double-Gate Carbon Nanotubes, Sublithographic Nanowires, Lithographic Crossbar arrangements). Novel architectural organizations, as well as the associated tools, are presented in order to explore this freshly opened design space.

This book provides an in-depth overview of on chip instrumentation technologies and various approaches taken in adding instrumentation to System on Chip (ASIC, ASSP, FPGA, etc.) design that are collectively becoming known as Design for Debug (DfD). On chip instruments are hardware based blocks that are added to a design for the specific purpose and improving the visibility of internal or embedded portions of the design (specific instruction flow in a processor, bus transaction in an on chip bus as examples) to improve the analysis or optimization capabilities for a SoC. DfD is the methodology and infrastructure that surrounds the instrumentation. Coverage includes specific design examples and discussion of implementations and DfD tradeoffs in a decision to design or select instrumentation or SoC that include instrumentation. Although the focus will be on hardware implementations, software and tools will be discussed in some detail.

The appropriate interconnect model has changed several times over the past two decades due to the application of aggressive technology scaling. New, more accurate interconnect models are required to manage the changing physical characteristics of integrated circuits. Currently, RC models are used to analyze high resistance nets while capacitive models are used for less resistive interconnect. However, on-chip inductance is becoming more important with integrated circuits operating at higher frequencies, since the inductive impedance is proportional to the frequency. The operating frequencies of integrated circuits have increased dramatically over the past decade and are expected to maintain the same rate of increase over the next decade, approaching 10 GHz by the year 2012. Also, wide wires are frequently encountered in important global nets, such as clock distribution networks and in upper metal layers, and performance requirements are pushing the introduction of new materials for low resistance interconnect, such as copper interconnect already used in many commercial CMOS technologies. On-Chip Inductance in High Speed Integrated Circuits deals with the design and analysis of integrated circuits with a specific focus on on-chip inductance effects. It has been described throughout this book that inductance can have a tangible effect on current high speed integrated circuits. For example, neglecting inductance and using an RC interconnect model in a production 0.25 mum CMOS technology can cause large errors (over 35%) in estimates of the propagation delay of on-chip interconnect. It has also been shown that including inductance in the repeater insertion design process as compared to using an RC model improves the overall repeater solution in terms of area, power, and delay with average savings of 40.8%, 15.6%, and 6.7%, respectively. On-Chip Inductance in High Speed Integrated Circuits is full of design and analysis techniques for RLC interconnect. These techniques are compared to techniques traditionally used for RC interconnect design to emphasize the effect of inductance. On-Chip Inductance in High Speed Integrated Circuits will be of interest to researchers in the area of high frequency interconnect, noise, and high performance integrated circuit design.

Research in analog integrated circuits has recently gone in the direction of low-voltage (LV), low-power (LP) design, especially in the environment of portable systems where a low supply voltage, given by a single-cell battery, is used. These LV circuits have to show a reduced power consumption to maintain a longer battery lifetime as well. In this area, traditional voltage-mode techniques are going to be substituted by the current-mode approach, which has the recognized advantage to overcome the gain-bandwidth product limitation, typical of operational amplifiers. Then they do not require high voltage gains and have good performance in terms of speed, bandwidth and accuracy. Inside the current-mode architectures, the current-conveyor (CCII) can be considered the basic circuit block because all the active devices can be made of a suitable connection of one or two CCIIs. CCII is particularly attractive in portable systems, where LV LP constraints have to be taken into account. In fact, it suffers less from the limitation of low current utilisation, while showing full dynamic characteristics at reduced supplies (especially CMOS version) and good high frequency performance. Recent advances in integrated circuit technology have also highlighted the usefulness of CCII solutions in a large number of signal processing applications.
In Low Voltage, Low Power CMOS Current Conveyors, the authors start by giving a brief history of the first and second generation CC. Then, the second generation current-conveyor (CCII) will be considered as a building block in the main active feedback devices and in the implementation of simple analog functions, as an alternative to OA. In the next chapters, thedesign of CCII topologies will be considered, together with a further look into CCII modern solutions and future trends. The authors will, therefore, describe LV LP CCII implementations, their evolution towards differential and generalized topologies, and new possible CCII applications in some basic analog functions such as filters, impedance simulators and converters, oscillators, among others.
Being a concise and modern book on current conveyors, Low Voltage, Low Power CMOS Current Conveyors considers these kinds of devices both in a general environment and for low-voltage low-power applications. This book can constitute an excellent reference for analog designers and researchers and is suitable for use as a textbook in an advanced course on Microelectronics.

This book presents the latest techniques for characterization, modeling and design for nano-scale non-volatile memory (NVM) devices. Coverage focuses on fundamental NVM device fabrication and characterization, internal state identification of memristic dynamics with physics modeling, NVM circuit design and hybrid NVM memory system design-space optimization. The authors discuss design methodologies for nano-scale NVM devices from a circuits/systems perspective, including the general foundations for the fundamental memristic dynamics in NVM devices. Coverage includes physical modeling, as well as the development of a platform to explore novel hybrid CMOS and NVM circuit and system design. * Offers readers a systematic and comprehensive treatment of emerging nano-scale non-volatile memory (NVM) devices; * Focuses on the internal state of NVM memristic dynamics, novel NVM readout and memory cell circuit design and hybrid NVM memory system optimization; * Provides both theoretical analysis and practical examples to illustrate design methodologies; * Illustrates design and analysis for recent developments in spin-toque-transfer, domain-wall racetrack and memristors.

A unique text on the theory and design fundaments of inductors and transformers, updated with more coverage on the optimization of magnetic devices and many new design examples The first edition is popular among a very broad audience of readers in different areas of engineering and science. This book covers the theory and design techniques of the major types of high-frequency power inductors and transformers for a variety of applications, including switching-mode power supplies (SMPS) and resonant dc-to-ac power inverters and dc-to-dc power converters. It describes eddy-current phenomena (such as skin and proximity effects), high-frequency magnetic materials, core saturation, core losses, complex permeability, high-frequency winding resistance, winding power losses, optimization of winding conductors, integrated inductors and transformers, PCB inductors, self-capacitances, self-resonant frequency, core utilization factor area product method, and design techniques and procedures of power inductors and transformers. These components are commonly used in modern power conversion applications. The material in this book has been class-tested over many years in the author s own courses at Wright State University, which have a high enrolment of about a hundred graduate students per term. The book presents the growing area of magnetic component research in a textbook form, covering the foundations for analysing and designing magnetic devices specifically at high-frequencies. Integrated inductors are described, and the Self-capacitance of inductors and transformers is examined. This new edition adds information on the optimization of magnetic components (Chapter 5). Chapter 2 has been expanded to provide better coverage of core losses and complex permeability, and Chapter 9 has more in-depth coverage of self-capacitances and self-resonant frequency of inductors. There is a more rigorous treatment of many concepts in all chapters. Updated end-of-chapter problems aid the readers learning process, with an online solutions manual available for use in the classroom. * Provides physics-based descriptions and models of discrete inductors and transformers as well as integrated magnetic devices * New coverage on the optimization of magnetic devices, updated information on core losses and complex permeability, and more in-depth coverage of self-capacitances and self-resonant frequency of inductors * Many new design examples and end-of-chapter problems for the reader to test their learning * Presents the most up-to-date and important references in the field * Updated solutions manual, now available through a companion website An up to date resource for Post-graduates and professors working in electrical and computer engineering. Research students in power electronics. Practising design engineers of power electronics circuits and RF (radio-frequency) power amplifiers, senior undergraduates in electrical and computer engineering, and R & D staff.

Software Defined Radio makes wireless communications easier, more efficient, and more reliable. This book bridges the gap between academic research and practical implementation. When beginning a project, practicing engineers, technical managers, and graduate students can save countless hours by considering the concepts presented in these pages.The author covers the myriad options and trade-offs available when selecting an appropriate hardware architecture.As demonstrated here, the choice between hardware- and software-centric architecture can mean the difference between meeting an aggressive schedule and bogging down in endless design iterations.Because of the author's experience overseeing dozens of failed and successful developments, he is able to present many real-life examples.Some of the key concepts covered are: Choosing the right architecture for the market - laboratory, military, or commercial, Hardware platforms - FPGAs, GPPs, specialized and hybrid devices, Standardization efforts to ensure interoperability and portabilitym State-of-the-art components for radio frequency, mixed-signal, and baseband processing.

The text requires only minimal knowledge of wireless communications; whenever possible, qualitative arguments are used instead of equations.An appendix provides a quick overview of wireless communications and introduces most of the concepts the readers will need to take advantage of the material.An essential introduction to SDR, this book is sure to be an invaluable addition to any technical bookshelf."

Research on real-time Java technology has been prolific over the past decade, leading to a large number of corresponding hardware and software solutions, and frameworks for distributed and embedded real-time Java systems. This book is aimed primarily at researchers in real-time embedded systems, particularly those who wish to understand the current state of the art in using Java in this domain. Much of the work in real-time distributed, embedded and real-time Java has focused on the Real-time Specification for Java (RTSJ) as the underlying base technology, and consequently many of the Chapters in this book address issues with, or solve problems using, this framework.Describes innovative techniques in: scheduling, memory management, quality of service and communication systems supporting real-time Java applications;Includes coverage of multiprocessor embedded systems and parallel programming;Discusses state-of-the-art resource management for embedded systems, including Java's real-time garbage collection and parallel collectors;Considers hardware support for the execution of Java programs including how programs can interact with functional accelerators;Includes coverage of Safety Critical Java for development of safety critical embedded systems."

This book explores the design implications of emerging, non-volatile memory (NVM) technologies on future computer memory hierarchy architecture designs. Since NVM technologies combine the speed of SRAM, the density of DRAM, and the non-volatility of Flash memory, they are very attractive as the basis for future universal memories. This book provides a holistic perspective on the topic, covering modeling, design, architecture and applications. The practical information included in this book will enable designers to exploit emerging memory technologies to improve significantly the performance/power/reliability of future, mainstream integrated circuits.

This work provides a comprehensive discussion of the bias dependence of equivalent circuit parameters for the three devices and an extensive discussion of temperature dependence. It: covers recess-etched MESFETs and self-aligned MESFETs with and without lightly-doped-drains and JFETs; analyzes GaAs-based pHEMTS and InP lattice-matched HEMT equivalent circuits; and describes a large-signal, temperature-dependent model extractor for A1GaAs-GaAs HBTs. The book is intended for circuit designers, process and device developers and test engineers.

In recent years, there has been considerable interest in highly integrated, low power, portable wireless devices. This monograph focuses on the problem of low power GFSK/GMSK modulation and presents an architectural approach for improved performance. Including several valuable tools for the practicing engineer.

Wireless communication has emerged as an independent discipline in the past decades. Everything from cellular voice telephony to wireless data transmission using wireless sensor networks has profoundly impacted the safety, production, and productivity of industries and our lifestyle as well. After a decade of exponential growth, the wireless industry is one of the largest industries in the world. Therefore, it would be an injustice if the wireless communication is not explored for mining industry. Underground mines, which are characterized by their tough working conditions and hazardous environments, require fool-proof mine-wide communication systems for smooth functioning of mine workings and ensuring better safety. Proper and re- able communication systems not only save the machine breakdown time but also help in immediate passing of messages from the vicinity of underground working area to the surface for day-to-day normal mining operations as well as for speedy rescue operations in case of disaster. Therefore, a reliable and effective commu- cation system is an essential requisite for safe working, and maintaining requisite production and productivity of underground mines. Most of the existing systems generally available in underground mines are based on line (wired) communication principle, hence these are unable to withstand in the disaster conditions and dif?cult to deploy in inaccessible places. Therefore, wireless communication is an indispe- able, reliable, and convenient system and essential in case of day-to-day normal duty or disaster situations.

This book provides a complete overview of significant design challenges in respect to circuit miniaturization and power reduction of the neural recording system, along with circuit topologies, architecture trends, and (post-silicon) circuit optimization algorithms. The introduced novel circuits for signal conditioning, quantization, and classification, as well as system configurations focus on optimized power-per-area performance, from the spatial resolution (i.e. number of channels), feasible wireless data bandwidth and information quality to the delivered power of implantable system.

Microelectromechanical Systems (MEMS) stand poised for the next major breakthrough in the silicon revolution that began with the transistor in the 1960s and has revolutionized microelectronics. MEMS allow one to not only observe and process information of all types from small scale systems, but also to affect changes in systems and the environment at that scale. "RF MEMS Switches and Integrated Switching Circuits" builds on the extensive body of literature that exists in research papers on analytical and numerical modeling and design based on RF MEMS switches and micromachined switching circuits, and presents a unified framework of coverage. This volume includes, but is not limited to, RF MEMS approaches, developments from RF MEMS switches to RF switching circuits, and MEMS switch components in circuit systems. This book also: -Presents RF Switches and switching circuit MEMS devices in a unified framework covering all aspects of engineering innovation, design, modeling, fabrication, control and experimental implementation -Discusses RF switch devices in detail, with both system and component-level circuit integration using micro- and nano-fabrication techniques -Includes an emphasis on design innovation and experimental relevance rather than basic electromagnetic theory and device physics "RF MEMS Switches and Integrated Switching Circuits" is perfect for engineers, researchers and students working in the fields of MEMS, circuits and systems and RFs.

Cellular Neural Networks (CNNs) constitute a class of nonlinear, recurrent and locally coupled arrays of identical dynamical cells that operate in parallel. ANALOG chips are being developed for use in applications where sophisticated signal processing at low power consumption is required. Signal processing via CNNs only becomes efficient if the network is implemented in analog hardware. In view of the physical limitations that analog implementations entail, robust operation of a CNN chip with respect to parameter variations has to be insured. By far not all mathematically possible CNN tasks can be carried out reliably on an analog chip; some of them are inherently too sensitive. This book defines a robustness measure to quantify the degree of robustness and proposes an exact and direct analytical design method for the synthesis of optimally robust network parameters. The method is based on a design centering technique which is generally applicable where linear constraints have to be satisfied in an optimum way. Processing speed is always crucial when discussing signal-processing devices. In the case of the CNN, it is shown that the setting time can be specified in closed analytical expressions, which permits, on the one hand, parameter optimization with respect to speed and, on the other hand, efficient numerical integration of CNNs. Interdependence between robustness and speed issues are also addressed. Another goal pursued is the unification of the theory of continuous-time and discrete-time systems. By means of a delta-operator approach, it is proven that the same network parameters can be used for both of these classes, even if their nonlinear output functions differ. More complex CNN optimization problems that cannot be solved analytically necessitate resorting to numerical methods. Among these, stochastic optimization techniques such as genetic algorithms prove their usefulness, for example in image classification problems. Since the inception of the CNN, the problem of finding the network parameters for a desired task has been regarded as a learning or training problem, and computationally expensive methods derived from standard neural networks have been applied. Furthermore, numerous useful parameter sets have been derived by intuition. In this book, a direct and exact analytical design method for the network parameters is presented. The approach yields solutions which are optimum with respect to robustness, an aspect which is crucial for successful implementation of the analog CNN hardware that has often been neglected. This beautifully rounded work provides many interesting and useful results, for both CNN theorists and circuit designers.' Leon O. Chua

Improving the performance of existing technologies has always been a focal practice in the development of computational systems. However, as circuitry is becoming more complex, conventional techniques are becoming outdated and new research methodologies are being implemented by designers. Performance Optimization Techniques in Analog, Mix-Signal, and Radio-Frequency Circuit Design features recent advances in the engineering of integrated systems with prominence placed on methods for maximizing the functionality of these systems. This book emphasizes prospective trends in the field and is an essential reference source for researchers, practitioners, engineers, and technology designers interested in emerging research and techniques in the performance optimization of different circuit designs.