This unique book provides an up-to-date overview of the concepts behind lead-free soldering techniques. Readers will find a description of the physical and mechanical properties of lead-free solders, in addition to lead-free electronics and solder alloys. Additional topics covered include the reliability of lead-free soldering, tin whiskering and electromigration, in addition to emerging technologies and research.

This book introduces readers to the design of adaptive equalization solutions integrated in standard CMOS technology for high-speed serial links. Since continuous-time equalizers offer various advantages as an alternative to discrete-time equalizers at multi-gigabit rates, this book provides a detailed description of continuous-time adaptive equalizers design - both at transistor and system levels-, their main characteristics and performances. The authors begin with a complete review and analysis of the state of the art of equalizers for wireline applications, describing why they are necessary, their types, and their main applications. Next, theoretical fundamentals of continuous-time adaptive equalizers are explored. Then, new structures are proposed to implement the different building blocks of the adaptive equalizer: line equalizer, loop-filters, power comparator, etc. The authors demonstrate the design of a complete low-power, low-voltage, high-speed, continuous-time adaptive equalizer. Finally, a cost-effective CMOS receiver which includes the proposed continuous-time adaptive equalizer is designed for 1.25 Gb/s optical communications through 50-m length, 1-mm diameter plastic optical fiber (POF).

This book describes for readers technology used for effective sensing of our physical world and intelligent processing techniques for sensed information, which are essential to the success of Internet of Things (IoTs). The authors provide a multidisciplinary view of sensor technology from materials, process, circuits, and big data domains and showcase smart sensor systems in real applications including smart home, transportation, medical, environmental, agricultural, etc. Unlike earlier books on sensors, this book will provide a "global" view on smart sensors covering abstraction levels from device, circuit, systems, and algorithms. Profiles active research on smart sensors based on CMOS microelectronics; Describes applications of sensors and sensor systems in cyber physical systems, the social information infrastructure in our modern world; Includes coverage of a variety of related information technologies supporting the application of sensors; Discusses the integration of computation, networking, actuation, databases, and various sensors, in order to embed smart sensor systems into actual social systems.

During the last decade, many new concepts have been proposed for improving the performance of power rectifiers and transistors. The results of this research are dispersed in the technical literature among journal articles and abstracts of conferences. Consequently, the information is not readily available to researchers and practicing engineers in the power device community. There is no cohesive treatment of the ideas to provide an assessment of the relative merits of the ideas.

Advanced Power Rectifier Concepts provides an in-depth treatment of the physics of operation of advanced power rectifiers. Analytical models for explaining the operation of all the advanced power rectifier devices will be developed. The results off numerical simulations will be provided to provide additional insight into the device physics and validate the analytical models. The results of two-dimensional simulations will be provided to corroborate the analytical models and provide greater insight into the device operation.

During the last one and a half decades, wireless sensor networks have witnessed significant growth and tremendous development in both academia and industry. A large number of researchers, including computer scientists and engineers, have been interested in solving challenging problems that span all the layers of the protocol stack of sensor networking systems. Several venues, such as journals, conferences, and workshops, have been launched to cover innovative research and practice in this promising and rapidly advancing field. Because of these trends, I thought it would be beneficial to provide our sensor networks community with a comprehensive reference on as much of the findings as possible on a variety of topics in wireless sensor networks. As this area of research is in continuous progress, it does not seem to be a reasonable solution to keep delaying the publication of such reference any more. This book relates to the second volume and focuses on the advanced topics and applications of wireless sensor networks. Our rationale is that the second volume has all application-specific and non-conventional sensor networks, emerging techniques and advanced topics that are not as matured as what is covered in the first volume. Thus, the second volume deals with three-dimensional, underground, underwater, body-mounted, and societal networks. Following Donald E. Knuth's above-quoted elegant strategy to focus on several important fields (The Art of Computer Programming: Fundamental Algorithms, 1997), all the book chapters in this volume include up-to-date research work spanning various topics, such as stochastic modeling, barrier and spatiotemporal coverage, tracking, estimation, counting, coverage and localization in three-dimensional sensor networks, topology control and routing in three-dimensional sensor networks, underground and underwater sensor networks, multimedia and body sensor networks, and social sensing. Most of these major topics can be covered in an advanced course on wireless sensor networks. This book will be an excellent source of information for graduate students majoring in computer science, computer engineering, electrical engineering, or any related discipline. Furthermore, computer scientists, researchers, and practitioners in both academia and industry will find this book useful and interesting.

This book is addressed to newcomers to error control coding (ECC), making the subject easy to understand and to apply in a variety of cases. The book begins by presenting in a detailed, step-by-step manner the plethora of parts an ECC system has and the way they interact to achieve the performance required. Contrary to the more abstract and formal approach followed in most books on this topic, this book is unique in that all of the concepts, methods, techniques and algorithms are introduced by way of examples. Thus, the book is almost a workbook, and therefore very suitable for self-study. Readers are encouraged to take an active role while reading, performing calculations as chapters' progress. Moreover, to reinforce the learning process, many of the topics introduced in the book (Galois fields, Extended Hamming codes, Reed-Solomon codes, interleaving, erasure correction, etc.) are presented in various parts of the book in different ways or contexts. Offers a practical guide to error control coding, accessible to readers with varying backgrounds; Provides newcomers with a sound foundation in error control coding, using a select few topics considered by the author fundamental from an engineering point of view; Presents material with minimal mathematics; Motivates carefully concepts, methods and algorithms making clear the idea behind the conditions for the code to work.

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance.
Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed.
This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.
* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult tofind;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.

This book describes a new way to design and utilize Instrumentation Amplifiers (IAs) by taking advantages of the current-mode (CM) approach. For the first time, all different topologies of CMIAs are discussed and compared, providing a single-source reference for instrumentation and measurement experts who want to choose a topology for a specific application. The authors also explain major challenges in designing CMIAs, so the book can be useful for anyone studying instrumentation amplifiers, and even other analog circuits. Coverage also includes various CM signal processing techniques employed in CMIAs, and applications of the CMIAs in biomedical and data acquisition are demonstrated.

This book includes a selection of the best contributions to the Forum on Specification and Design Languages held in 2005 (FDL'05). It provides detailed insights into recent works dealing with a large spectrum of issues in system-on-chip design. All the chapters have been carefully revised and extended to offer up-to-date information. They also provide seeds for further researches and developments in the field of heterogeneous systems-on-chip design.

Power consumption becomes the most important design goal in a wide range of electronic systems. There are two driving forces towards this trend: continuing device scaling and ever increasing demand of higher computing power. First, device scaling continues to satisfy Moore's law via a conventional way of scaling (More Moore) and a new way of exploiting the vertical integration (More than Moore). Second, mobile and IT convergence requires more computing power on the silicon chip than ever. Cell phones are now evolving towards mobile PC. PCs and data centers are becoming commodities in house and a must in industry. Both supply enabled by device scaling and demand triggered by the convergence trend realize more computation on chip (via multi-core, integration of diverse functionalities on mobile SoCs, etc.) and finally more power consumption incurring power-related issues and constraints.

"Energy-Aware System Design: Algorithms and Architectures" provides state-of-the-art ideas for low power design methods from circuit, architecture to software level andoffers design case studies in three fast growing areas of mobile storage, biomedical and security.

Important topics and features:

- Describes very recent advanced issues and methods for energy-aware design at each design level from circuit andarchitecture toalgorithm level, and also covering important blocks including low power main memory subsystem and on-chip network at architecture level

- Explains efficient power conversion and delivery which is becoming important as heterogeneous power sources are adopted for digital and non-digital parts

- Investigates 3D die stacking emphasizing temperature awareness for better perspective on energy efficiency

- Presents three practical energy-aware design case studies; novel storage device (e.g., solid state disk), biomedical electronics (e.g., cochlear and retina implants), and wireless surveillance camera systems.

Researchers and engineers in the field of hardware and software design will find this book an excellent starting point to catch up with the state-of-the-art ideas of low power design.

This book is the second of two volumes addressing the design challenges associated with new generations of semiconductor technology. The various chapters are compiled from tutorials presented at workshops in recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip.

Many and ever more mobile users wish to enjoy a variety of multimedia services, in very diverse geographical environments. The growing number of communication options within and across wireless standards is accommodating the growing volume and heterogeneity in wireless wishes. On the other hand, advancement in radio technologies opening much more flexibility, a.o. through Software Defined Radios, opens up the possibility to realize mobile devices featuring multi-mode options at low cost and interesting form factors.

It is crucial to manage the new degrees of freedom opened up in radios and standards in a smart way, such that the required service is offered at satisfactory quality as efficiently as possible. Efficiency in energy consumption is clearly primordial for battery powered mobile terminals specifically, and in the context of growing ecological concerns in a broader context. Moreover, efficient usage of the spectrum is a growing prerequisite for wireless systems, and coexistence of different standards puts overall throughput at risk.

The management of flexibility risks bringing about intolerable complexity and hamper the desired agility. A systematic approach, consisting of anticipative preparing for smooth operation, allows mastering this challenge. Case studies show that already today, this approach enables smart operation of radios realizing impressive efficiency gains without hampering Quality-of-Service. In the future wireless communication scenes will be able to profit form the opening of the spectrum. Even smarter and cognitive behavior will become possible and essential.

This book presents a new set of embedded system design techniques called multidimensional data flow, which combine the various benefits offered by existing methodologies such as block-based system design, high-level simulation, system analysis and polyhedral optimization. It describes a novel architecture for efficient and flexible high-speed communication in hardware that can be used both in manual and automatic system design and that offers various design alternatives, balancing achievable throughput with required hardware size. This book demonstrates multidimensional data flow by showing its potential for modeling, analysis, and synthesis of complex image processing applications. These applications are presented in terms of their fundamental properties and resulting design constraints. Coverage includes a discussion of how far the latter can be met better by multidimensional data flow than alternative approaches. Based on these results, the book explains the principles of fine-grained system level analysis and high-speed communication synthesis. Additionally, an extensive review of related techniques is given in order to show their relation to multidimensional data flow.

This book provides a comprehensive overview of current research on memristors, memcapacitors and, meminductors. In addition to an historical overview of the research in this area, coverage includes the theory behind memristive circuits, as well as memcapacitance, and meminductance. Details are shown for recent applications of memristors for resistive random access memories, neuromorphic systems and hybrid CMOS/memristor circuits. Methods for the simulation of memristors are demonstrated and an introduction to neuromorphic modeling is provided.

An effective and cost efficient protection of electronic system against ESD stress pulses specified by IEC 61000-4-2 is paramount for any system design. This pioneering book presents the collective knowledge of system designers and system testing experts and state-of-the-art techniques for achieving efficient system-level ESD protection, with minimum impact on the system performance. All categories of system failures ranging from 'hard' to 'soft' types are considered to review simulation and tool applications that can be used. The principal focus of System Level ESD Co-Design is defining and establishing the importance of co-design efforts from both IC supplier and system builder perspectives. ESD designers often face challenges in meeting customers' system-level ESD requirements and, therefore, a clear understanding of the techniques presented here will facilitate effective simulation approaches leading to better solutions without compromising system performance. With contributions from Robert Ashton, Jeffrey Dunnihoo, Micheal Hopkins, Pratik Maheshwari, David Pomerenke, Wolfgang Reinprecht, and Matti Usumaki, readers benefit from hands-on experience and in-depth knowledge in topics ranging from ESD design and the physics of system ESD phenomena to tools and techniques to address soft failures and strategies to design ESD-robust systems that include mobile and automotive applications. The first dedicated resource to system-level ESD co-design, this is an essential reference for industry ESD designers, system builders, IC suppliers and customers and also Original Equipment Manufacturers (OEMs). Key features: * Clarifies the concept of system level ESD protection. * Introduces a co-design approach for ESD robust systems. * Details soft and hard ESD fail mechanisms. * Detailed protection strategies for both mobile and automotive applications. * Explains simulation tools and methodology for system level ESD co-design and overviews available test methods and standards. * Highlights economic benefits of system ESD co-design.

This book describes a new type of passive electronic components, called fractal elements, from a theoretical and practical point of view. The authors discuss in detail the physical implementation and design of fractal devices for application in fractional-order signal processing and systems. The concepts of fractals and fractal signals are explained, as well as the fundamentals of fractional calculus. Several implementations of fractional impedances are discussed, along with comparison of their performance characteristics. Details of design, schematics, fundamental techniques and implementation of RC-based fractal elements are provided.

RF and Microwave Microelectronics Packaging presents the latest developments in packaging for high-frequency electronics. It will appeal to practicing engineers in the electronic packaging and high-frequency electronics fields and to academic researchers interested in understanding leading issues in the commercial sector. It covers the latest developments in thermal management, electrical/RF/thermal-mechanical designs and simulations, packaging and processing methods as well as other RF/MW packaging-related fields.

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.
This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.
KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects.

The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages:

Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT);Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly;Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model;Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.

"

At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure.

This book presents a tutorial review of van der Pol model, a universal oscillator model for the analysis of modern RC oscillators in weak and strong nonlinear regimes. A detailed analysis of the injection locking in van der Pol oscillators is also presented. The relation between the van der Pol parameters and several circuit implementations in CMOS nanotechnology is given, showing that this theory is very useful in the optimization of oscillator key parameters, such as: frequency, amplitude and phase relationship. The authors discuss three different examples: active coupling RC oscillators, capacitive coupling RC oscillators, and two-integrator oscillator working in the sinusoidal regime. * Provides a detailed tutorial on the van der Pol oscillator model, which can be the basis for the analysis of modern RC oscillators in weak and strong nonlinear regimes; * Demonstrations the relationship between the van der Pol parameters and several circuit implementations in CMOS nanotechnology, showing that this theory is a powerful tool in the optimization of key oscillator parameters; * Provides three circuit prototypes implemented in modern CMOS nanotechnology in the GHz range, with applications in low area, low power, low cost, wireless sensor network (WSN) applications (e.g. IoT, BLE).

This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications. A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13um RF CMOS technology for use in highly-linear, low-cost UWB Radio-over-Fiber communication systems."

This volume gives the latest developments in on the mechanisms of cancer cell resistance to apoptotic stimuli, which eventually result in cancer progression and metastasis. One of the main challenges in cancer research is to develop new therapies to combat resistant tumors. The development of new effective therapies will be dependent on delineating the biochemical, molecular, and genetic mechanisms that regulate tumor cell resistance to cytotoxic drug-induced apoptosis. These mechanisms should reveal gene products that directly regulate resistance in order to develop new drugs that target these resistance factors and such new drugs may either be selective or common to various cancers. If successful, new drugs may not be toxic and may be used effectively in combination with subtoxic conventional drugs to achieve synergy and to reverse tumor cell resistance. The research developments presented in this book can be translated to produce better clinical responses to resistant tumors.

This book shares with readers practical design knowledge gained from the author's 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds.

Model based testing is the most powerful technique for testing hardware and software systems. Models in Hardware Testing describes the use of models at all the levels of hardware testing. The relevant fault models for nanoscaled CMOS technology are introduced, and their implications on fault simulation, automatic test pattern generation, fault diagnosis, memory testing and power aware testing are discussed. Models and the corresponding algorithms are considered with respect to the most recent state of the art, and they are put into a historical context by a concluding chapter on the use of physical fault models in fault tolerance.