Despite the recent development and interest in the photonics of metallic wire structures, the relatively simple concepts and physics often remain obscured or poorly explained to those who do not specialize in the field. Electromagnetic Behaviour of Metallic Wire Structures provides a clear and coherent guide to understanding these phenomena without excessive numerical calculations. Including both background material and detailed derivations of the various different formulae applied, Electromagnetic Behaviour of Metallic Wire Structures describes how to extend basic circuit theory relating to voltages, currents, and resistances of metallic wire networks to include situations where the currents are no longer spatially uniform along the wire. This lays a foundation for a deeper understanding of the many new phenomena observed in meta-electromagnetic materials. Examples of applications are included to support this new approach making Electromagnetic Behaviour of Metallic Wire Structures a comprehensive and self-contained volume suitable for use by specialists, non-specialist, researchers and professionals in other relevant fields and even students.

This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.

Automatic Performance Tuning is a new software paradigm which enables software to be high performance in any computing environment. Its methodologies have been developed over the past decade, and it is now rapidly growing in terms of its scope and applicability, as well as in its scientific knowledge and technological methods. Software developers and researchers in the area of scientific and technical computing, high performance database systems, optimized compilers, high performance systems software, and low-power computing will find this book to be an invaluable reference to this powerful new paradigm.

Lead-free solders are used extensively as interconnection materials in electronic assemblies and play a critical role in the global semiconductor packaging and electronics manufacturing industry. Electronic products such as smart phones, notebooks and high performance computers rely on lead-free solder joints to connect IC chip components to printed circuit boards." Lead Free Solder: Mechanics and Reliability" provides in-depth design knowledge on lead-free solder elastic-plastic-creep and strain-rate dependent deformation behavior and its application in failure assessment of solder joint reliability. It includes coverage of advanced mechanics of materials theory and experiments, mechanical properties of solder and solder joint specimens, constitutive models for solder deformation behavior; numerical modeling and simulation of solder joint failure subject to thermal cycling, mechanical bending fatigue, vibration fatigue and board-level drop impact tests.

According to the Semiconductor Industry Association's 1999 International Technology Roadmap for Semiconductors, by the year 2008 the integration of more than 500 million transistors will be possible on a single chip. Integrating transistors on silicon will depend increasingly on design reuse.

Design reuse techniques have become the subject of books, conferences, and podium discussions over the last few years. However, most discussions focus on higher-level abstraction like RTL descriptions, which can be synthesized. Design reuse is often seen as an add-on to normal design activity, or a special design task that is not an integrated part of the existing design flow. This may all be true for the ASIC world, but not for high-speed, high-performance microprocessors.

In the field of high-speed microprocessors, design reuse is an integrated part of the design flow. The method of choice in this demanding field was, and is always, physical design reuse at the layout level. In the past, the practical implementations of this method were linear shrinks and the lambda approach. With the scaling of process technology down to 0.18 micron and below, this approach lost steam and became inefficient.
The only viable solution is a method, which is now called Automatic Layout Modification (ALM). It combines compaction, mask manipulation, and correction with powerful capabilities.

Automatic Layout Modification, Including design reuse of the Alpha CPU in 0.13 micron SOI technology is a welcome effort to improving some of the practices in chip design today. It is a comprehensive reference work on Automatic Layout Modification which will be valuable to VLSI courses at universities, and to CAD and circuit engineers and engineering managers.

This book describes new, fuzzy logic-based mathematical apparatus, which enable readers to work with continuous variables, while implementing whole circuit simulations with speed, similar to gate-level simulators and accuracy, similar to circuit-level simulators. The author demonstrates newly developed principles of digital integrated circuit simulation and optimization that take into consideration various external and internal destabilizing factors, influencing the operation of digital ICs. The discussion includes factors including radiation, ambient temperature, electromagnetic fields, and climatic conditions, as well as non-ideality of interconnects and power rails.

CMOS Test and Evaluation: A Physical Perspective is a single source for an integrated view of test and data analysis methodology for CMOS products, covering circuit sensitivities to MOSFET characteristics, impact of silicon technology process variability, applications of embedded test structures and sensors, product yield, and reliability over the lifetime of the product. This book also covers statistical data analysis and visualization techniques, test equipment and CMOS product specifications, and examines product behavior over its full voltage, temperature and frequency range.

This title deals with the design and analysis of log-domain filter circuits. It describes synthesis methods for developing bipolar or BiCMOS filter circuits with cut-off frequencies ranging from the low kilohertz range to several hundred megahertz. Numerous examples provide measured experimental data from IC prototypes.

Emerging Trends in Computing, Informatics, Systems Sciences, and Engineering includes a set of rigorously reviewed world-class manuscripts addressing and detailing state-of-the-art research projects in the areas of Industrial Electronics, Technology & Automation, Telecommunications and Networking, Systems, Computing Sciences and Software Engineering, Engineering Education, Instructional Technology, Assessment, and E-learning. This book includes the proceedings of the International Joint Conferences on Computer, Information, and Systems Sciences, and Engineering (CISSE 2010). The proceedings are a set of rigorously reviewed world-class manuscripts presenting the state of international practice in Innovative Algorithms and Techniques in Automation, Industrial Electronics and Telecommunications.

This book addresses reliability and energy efficiency of on-chip networks using cooperative error control. It describes an efficient way to construct an adaptive error control codec capable of tracking noise conditions and adjusting the error correction strength at runtime. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance.

This book presents the latest techniques for characterization, modeling and design for nano-scale non-volatile memory (NVM) devices. Coverage focuses on fundamental NVM device fabrication and characterization, internal state identification of memristic dynamics with physics modeling, NVM circuit design and hybrid NVM memory system design-space optimization. The authors discuss design methodologies for nano-scale NVM devices from a circuits/systems perspective, including the general foundations for the fundamental memristic dynamics in NVM devices. Coverage includes physical modeling, as well as the development of a platform to explore novel hybrid CMOS and NVM circuit and system design. * Offers readers a systematic and comprehensive treatment of emerging nano-scale non-volatile memory (NVM) devices; * Focuses on the internal state of NVM memristic dynamics, novel NVM readout and memory cell circuit design and hybrid NVM memory system optimization; * Provides both theoretical analysis and practical examples to illustrate design methodologies; * Illustrates design and analysis for recent developments in spin-toque-transfer, domain-wall racetrack and memristors.

This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions. The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost.

Current multimedia and telecom applications require complex, heterogeneous multiprocessor system on chip (MPSoC) architectures with specific communication infrastructure in order to achieve the required performance. Heterogeneous MPSoC includes different types of processing units (DSP, microcontroller, ASIP) and different communication schemes (fast links, non standard memory organization and access).

Programming an MPSoC requires the generation of efficient software running on MPSoC from a high level environment, by using the characteristics of the architecture. This task is known to be tedious and error prone, because it requires a combination of high level programming environments with low level software design.

This book gives an overview of concepts related to embedded software design for MPSoC. It details a full software design approach, allowing systematic, high-level mapping of software applications on heterogeneous MPSoC. This approach is based on gradual refinement of hardware/software interfaces and simulation models allowing to validate the software at different abstraction levels.

This book combines Simulink for high level programming and SystemC for the low level software development. This approach is illustrated with multiple examples of application software and MPSoC architectures that can be used for deep understanding of software design for MPSoC.

Sigma delta modulation has become a very useful and widely applied technique for high performance Analog-to-Digital (A/D) conversion of narrow band signals. Through the use of oversampling and negative feedback, the quantization errors of a coarse quantizer are suppressed in a narrow signal band in the output of the modulator. Bandpass sigma delta modulation is well suited for A/D conversion of narrow band signals modulated on a carrier, as occurs in communication systems such as AM/FM receivers and mobile phones. Due to the nonlinearity of the quantizer in the feedback loop, a sigma delta modulator may exhibit input signal dependent stability properties. The same combination of the nonlinearity and the feedback loop complicates the stability analysis. In Bandpass Sigma Delta Modulators, the describing function method is used to analyze the stability of the sigma delta modulator. The linear gain model commonly used for the quantizer fails to predict small signal stability properties and idle patterns accurately. In Bandpass Sigma Delta Modulators an improved model for the quantizer is introduced, extending the linear gain model with a phase shift. Analysis shows that the phase shift of a sampled quantizer is in fact a phase uncertainty. Stability analysis of sigma delta modulators using the extended model allows accurate prediction of idle patterns and calculation of small-signal stability boundaries for loop filter parameters. A simplified rule of thumb is derived and applied to bandpass sigma delta modulators. The stability properties have a considerable impact on the design of single-loop, one-bit, high-order continuous-time bandpass sigma delta modulators. The continuous-time bandpass loop filter structure should have sufficient degrees of freedom to implement the desired (small-signal stable) sigma delta modulator behavior. Bandpass Sigma Delta Modulators will be of interest to practicing engineers and researchers in the areas of mixed-signal and analog integrated circuit design.

This book provides an in-depth overview of on chip instrumentation technologies and various approaches taken in adding instrumentation to System on Chip (ASIC, ASSP, FPGA, etc.) design that are collectively becoming known as Design for Debug (DfD). On chip instruments are hardware based blocks that are added to a design for the specific purpose and improving the visibility of internal or embedded portions of the design (specific instruction flow in a processor, bus transaction in an on chip bus as examples) to improve the analysis or optimization capabilities for a SoC. DfD is the methodology and infrastructure that surrounds the instrumentation. Coverage includes specific design examples and discussion of implementations and DfD tradeoffs in a decision to design or select instrumentation or SoC that include instrumentation. Although the focus will be on hardware implementations, software and tools will be discussed in some detail.

History of the Book The last three decades have witnessed an explosive development in integrated circuit fabrication technologies. The complexities of cur rent CMOS circuits are reaching beyond the 100 nanometer feature size and multi-hundred million transistors per integrated circuit. To fully exploit this technological potential, circuit designers use sophisticated Computer-Aided Design (CAD) tools. While supporting the talents of innumerable microelectronics engineers, these CAD tools have become the enabling factor responsible for the successful design and implemen tation of thousands of high performance, large scale integrated circuits. This research monograph originated from a body of doctoral disserta tion research completed by the first author at the University of Rochester from 1994 to 1999 while under the supervision of Prof. Eby G. Friedman. This research focuses on issues in the design of the clock distribution net work in large scale, high performance digital synchronous circuits and particularly, on algorithms for non-zero clock skew scheduling. During the development of this research, it has become clear that incorporating timing issues into the successful integrated circuit design process is of fundamental importance, particularly in that advanced theoretical de velopments in this area have been slow to reach the designers' desktops."

This book serves as a practical guide for practicing engineers who need to design analog circuits for microelectronics. Readers will develop a comprehensive understanding of the basic techniques of analog modern electronic circuit design, discrete and integrated, application as sensors and control and data acquisition systems,and techniques of PCB design. * Describes fundamentals of microelectronics design in an accessible manner; * Takes a problem-solving approach to the topic, offering a hands-on guide for practicing engineers; * Provides realistic examples to inspire a thorough understanding of system-level issues, before going into the detail of components and devices; * Uses a new approach and provides several skills that help engineers and designers retain key and advanced concepts.

"Integrated 60GHz RF Beamforming in CMOS "describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters with other key building blocks such as low noise amplifiers and power amplifiers are described in detail. Finally, this book describes the integration of a 60GHz CMOS amplifier and an antenna in a printed circuit-board (PCB) package.

This Book and Simulation Software Bundle Project Dear Reader, this book project brings to you a unique study tool for ESD protection solutions used in analog-integrated circuit (IC) design. Quick-start learning is combined with in-depth understanding for the whole spectrum of cro- disciplinary knowledge required to excel in the ESD ?eld. The chapters cover technical material from elementary semiconductor structure and device levels up to complex analog circuit design examples and case studies. The book project provides two different options for learning the material. The printed material can be studied as any regular technical textbook. At the same time, another option adds parallel exercise using the trial version of a complementary commercial simulation tool with prepared simulation examples. Combination of the textbook material with numerical simulation experience presents a unique opportunity to gain a level of expertise that is hard to achieve otherwise. The book is bundled with simpli?ed trial version of commercial mixed- TM mode simulation software from Angstrom Design Automation. The DECIMM (Device Circuit Mixed-Mode) simulator tool and complementary to the book s- ulation examples can be downloaded from www.analogesd.com. The simulation examples prepared by the authors support the speci?c examples discussed across the book chapters. A key idea behind this project is to provide an opportunity to not only study the book material but also gain a much deeper understanding of the subject by direct experience through practical simulation examples.

Research on real-time Java technology has been prolific over the past decade, leading to a large number of corresponding hardware and software solutions, and frameworks for distributed and embedded real-time Java systems. This book is aimed primarily at researchers in real-time embedded systems, particularly those who wish to understand the current state of the art in using Java in this domain. Much of the work in real-time distributed, embedded and real-time Java has focused on the Real-time Specification for Java (RTSJ) as the underlying base technology, and consequently many of the Chapters in this book address issues with, or solve problems using, this framework.Describes innovative techniques in: scheduling, memory management, quality of service and communication systems supporting real-time Java applications;Includes coverage of multiprocessor embedded systems and parallel programming;Discusses state-of-the-art resource management for embedded systems, including Java's real-time garbage collection and parallel collectors;Considers hardware support for the execution of Java programs including how programs can interact with functional accelerators;Includes coverage of Safety Critical Java for development of safety critical embedded systems."

This book presents novel algorithms for designing Discrete-Time Sliding Mode Controllers (DSMCs) for Networked Control Systems (NCSs) with both types of fractional delays namely deterministic delay and random delay along with different packet loss conditions such as single packet loss and multiple packet loss that occur within the sampling period. Firstly, the switching type and non-switching type algorithms developed for the deterministic type fractional delay where the delay is compensated using Thiran's approximation technique. A modified discrete-time sliding surface is proposed to derive the discrete-time sliding mode control algorithms. The algorithm is further extended for the random fractional delay with single packet loss and multiple packet loss situations. The random fractional delay is modelled using Poisson's distribution function and packet loss is modelled by means of Bernoulli's function. The condition for closed loop stability in all above situations are derived using the Lyapunov function. Lastly, the efficacy of the proposed DSMC algorithms are demonstrated by extensive simulations and also experimentally validated on a servo system.

This book arises from experience the authors have gained from years of work as industry practitioners in the field of Electronic System Level design (ESL). At the heart of all things related to Electronic Design Automation (EDA), the core issue is one of models: what are the models used for, what should the models contain, and how should they be written and distributed. Issues such as interoperability and tool transportability become central factors that may decide which ones are successful and those that cannot get sufficient traction in the industry to survive.

Through a set of real examples taken from recent industry experience, this book will distill the state of the art in terms of System-Level Design models and provide practical guidance to readers that can be put into use. This book is an invaluable tool that will aid readers in their own designs, reduce risk in development projects, expand the scope of design projects, and improve developmental processes and project planning.

This book is about various adaptive and dynamic techniques used to optimize processor power and performance. It is based on a very successful forum at ISSCC which focused on Adaptive Techniques.

The book looks at the underlying process technology for adaptive designs and then examines different circuits, architecture and software that address the different aspects. The chapters are written by people both in academia and the industry to show the scope of alternative practices.

Combining ready-to-use programs, design formulas, design theory and optimization algorithms for linear microwave circuits, this book contains source code for the various programs cited in the text. A special floppy disk that contains the source code is available.

Research in analog integrated circuits has recently gone in the direction of low-voltage (LV), low-power (LP) design, especially in the environment of portable systems where a low supply voltage, given by a single-cell battery, is used. These LV circuits have to show a reduced power consumption to maintain a longer battery lifetime as well. In this area, traditional voltage-mode techniques are going to be substituted by the current-mode approach, which has the recognized advantage to overcome the gain-bandwidth product limitation, typical of operational amplifiers. Then they do not require high voltage gains and have good performance in terms of speed, bandwidth and accuracy. Inside the current-mode architectures, the current-conveyor (CCII) can be considered the basic circuit block because all the active devices can be made of a suitable connection of one or two CCIIs. CCII is particularly attractive in portable systems, where LV LP constraints have to be taken into account. In fact, it suffers less from the limitation of low current utilisation, while showing full dynamic characteristics at reduced supplies (especially CMOS version) and good high frequency performance. Recent advances in integrated circuit technology have also highlighted the usefulness of CCII solutions in a large number of signal processing applications.
In Low Voltage, Low Power CMOS Current Conveyors, the authors start by giving a brief history of the first and second generation CC. Then, the second generation current-conveyor (CCII) will be considered as a building block in the main active feedback devices and in the implementation of simple analog functions, as an alternative to OA. In the next chapters, thedesign of CCII topologies will be considered, together with a further look into CCII modern solutions and future trends. The authors will, therefore, describe LV LP CCII implementations, their evolution towards differential and generalized topologies, and new possible CCII applications in some basic analog functions such as filters, impedance simulators and converters, oscillators, among others.
Being a concise and modern book on current conveyors, Low Voltage, Low Power CMOS Current Conveyors considers these kinds of devices both in a general environment and for low-voltage low-power applications. This book can constitute an excellent reference for analog designers and researchers and is suitable for use as a textbook in an advanced course on Microelectronics.