Discusses process variation, model accuracy, design flow and many other practical engineering, reliability and manufacturing issues

Gives a good overview for a person who is not an expert in modeling and simulation, enabling them to extract the necessary information to competently use modeling and simulation programs

Written for engineering students and product design engineers

Existing sections in ESD Frim A to Z have been thoroughly revised and updated. New examples have been added to the troubleshooting chapter; and new versions of model specifications for ESD-safe handling and packaging can be found in the specifications chapter. The Appendix now includes ten recently published papers (making a total of 20) whose topics span the field of ESD control.

This book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques.

A Guide to VHDL, Second Edition is intended for the working engineer who needs to develop, document, simulate, and synthesize a design using the VHDL language. It is for system and chip designers who are working with VHDL CAD tools, and who have some experience programming in Fortran, Pascal, or C and have used a logic simulator. A Guide to VHDL, Second Edition includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises included in the chapters can be run to reinforce the learning experience. For practical purposes, this book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. A Guide to VHDL, Second Edition is designed as a primer and its contents are appropriate for an introductory course in VHDL. The VHDL language was updated in 1992 with some minor improvements. In most cases, the language is upward compatible. Although this book is based primarily on the VHDL 1987 standard, this new second edition indicates the significant changes in the 1992 language to assist the designer in writing upwardly compatible code.

On Optimal Interconnections for VLSI describes, from a geometric perspective, algorithms for high-performance, high-density interconnections during the global and detailed routing phases of circuit layout. First, the book addresses area minimization, with a focus on near-optimal approximation algorithms for minimum-cost Steiner routing. In addition to practical implementations of recent methods, the implications of recent results on spanning tree degree bounds and the method of Zelikovsky are discussed. Second, the book addresses delay minimization, starting with a discussion of accurate, yet algorithmically tractable, delay models. Recent minimum-delay constructions are highlighted, including provably good cost-radius tradeoffs, critical-sink routing algorithms, Elmore delay-optimal routing, graph Steiner arborescences, non-tree routing, and wiresizing. Third, the book addresses skew minimization for clock routing and prescribed-delay routing formulations. The discussion starts with early matching-based constructions and goes on to treat zero-skew routing with provably minimum wirelength, as well as planar clock routing. Finally, the book concludes with a discussion of multiple (competing) objectives, i.e., how to optimize area, delay, skew, and other objectives simultaneously. These techniques are useful when the routing instance has heterogeneous resources or is highly congested, as in FPGA routing, multi-chip packaging, and very dense layouts. Throughout the book, the emphasis is on practical algorithms and a complete self-contained development. On Optimal Interconnections for VLSI will be of use to both circuit designers (CAD tool users) as well as researchers and developers in the area of performance-driven physical design.

Smart and Flexible Digital-to-Analog Converters proposes new concepts and implementations for flexibility and self-correction of current-steering digital-to-analog converters (DACs) which allow the attainment of a wide range of functional and performance specifications, with a much reduced dependence on the fabrication process. DAC linearity is analysed with respect to the accuracy of the DAC unit elements. A classification is proposed of the many different current-steering DAC correction methods. The classification reveals methods that do not yet exist in the open literature. Further, this book systematically analyses self-calibration correction methods for the various DAC mismatch errors. For instance, efficient calibration of DAC binary currents is identified as an important missing method. This book goes on to propose a new methodology for correcting mismatch errors of both nominally identical unary as well as scaled binary DAC currents. A new concept for DAC flexibility is presented. The associated architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, functionality and performance. Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties.< DAC linearity is analysed with respect to the accuracy of the DAC unit elements. A classification is proposed of the many different current-steering DAC correction methods. The classification reveals methods that do not yet exist in the open literature. Further, this book systematically analyses self-calibration correction methods for the various DAC mismatch errors. For instance, efficient calibration of DAC binary currents is identified as an important missing method. This book goes on to propose a new methodology for correcting mismatch errors of both nominally identical unary as well as scaled binary DAC currents. A new concept for DAC flexibility is presented. The associated architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, functionality and performance. Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties. This book goes on to propose a new methodology for correcting mismatch errors of both nominally identical unary as well as scaled binary DAC currents. A new concept for DAC flexibility is presented. The associated architecture is based on a modular design approach that uses parallel sub-DAC units to realize flexible design, functionality and performance. Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties. Two main concepts, self-calibration and flexibility, are demonstrated in practice using three DAC testchips in 250nm, 180nm and 40nm standard CMOS. Smart and Flexible Digital-to-Analog Converters will be useful to both advanced professionals and newcomers in the field. Advanced professionals will find new methods that are fully elaborated from analysis at conceptual level to measurement results at test-chip level. New comers in the field will find structured knowledge of fully referenced state-of-the art methods with many fully explained novelties.

Asynchronous Pulse Logic is a comprehensive analysis of a newly developed asynchronous circuit family. The book covers circuit theory, practical circuits, design tools and an example of the design of a simple asynchronous microprocessor using the circuit family. Asynchronous Pulse Logic will be of interest to industrial and academic researcher working on high-speed VLSI systems. Graduate students will find this useful reference for computer-aided design of asynchronous or related VLSI systems.

This book mainly focuses on the investigation of the electric-field control of magnetism and spin-dependent transportation based on a Co40Fe40B20(CoFeB)/Pb(Mg1/3Nb2/3)0.7Ti0.3O3(PMN-PT) multiferroic heterostructure. Methods of characterization and analysis of the multiferroic properties with in situ electric fields are induced to detect the direct magnetoelectric (ME) coupling. A switchable and non-volatile electric field control of magnetization in CoFeB/PMN-PT(001) structures is observed at room temperature, and the mechanism of direct coupling between the ferroelectric domain and ferromagnetic film due to the combined action of 109 Degrees ferroelastic domain switching in PMN-PT and the absence of magnetocrystalline anisotropy in CoFeB is demonstrated. Moreover, the electric-field control of giant magnetoresistance is achieved in a CoFeB-based spin valve deposited on top of (011) oriented PMN-PT, which offers an avenue for implementing electric-writing and magnetic-reading random access memory at room temperature. Readers will learn the basic properties of multiferroic materials, many useful techniques related to characterizing multiferroics and the interesting ME effect in CoFeB/PMN-PT structures, which is significant for applications.

This book describes the analysis and design of precision temperature sensors in CMOS IC technology. It focusses on so-called smart temperature sensors, which provide a digital output signal that can be readily interpreted by a computer. The sensors described in this book are based on bipolar transistors, which are available as parasitic devices in standard CMOS technology. The relevant physical properties of these devices are described. It is shown in detail how their temperature characteristics can be used to obtain an accurate digital temperature reading. A sigma-delta converter plays a key role in the conversion to a digital output. Both the system-level design of such a converter, and the circuit-level implementation using both continuous-time and switched-capacitor techniques are described. Special attention is paid to the application of precision interfacing techniques, such as dynamic offset cancellation and dynamic element matching. A separate chapter is devoted to low-cost calibration techniques. Precision Temperature Sensors in CMOS Technology ends with a detailed description of three realized prototypes. The final prototype achieves an inaccuracy of only A0.1AC (3Sigma) over the temperature range of a "55AC to 125AC, which is the highest performance reported to date.

Through Silicon Via (TSV) is a key technology for realizing three-dimensional integrated circuits (3D ICs) for future high-performance and low-power systems with small form factors. This book covers both qualitative and quantitative approaches to give insights of modeling TSV in a various viewpoints such as signal integrity, power integrity and thermal integrity. Most of the analysis in this book includes simulations, numerical modelings and measurements for verification. The author and co-authors in each chapter have studied deep intoTSV for many years and the accumulated technical know-hows and tips for related subjects are comprehensively covered."

This book provides readers with a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It describes numerous "manufacturing-ready" GDSII-level layouts of TSV-based 3D ICs developed with the tools covered in the book. This book will also feature sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs. Full details of the related algorithms will be provided so that the readers will be able not only to grasp the core mechanics of the physical design tools, but also to be able to reproduce and improve upon the results themselves. This book will also offer various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process.

Adiabatic logic is a potential successor for static CMOS circuit design when it comes to ultra-low-power energy consumption. Future development like the evolutionary shrinking of the minimum feature size as well as revolutionary novel transistor concepts will change the gate level savings gained by adiabatic logic. In addition, the impact of worsening degradation effects has to be considered in the design of adiabatic circuits. The impact of the technology trends on the figures of merit of adiabatic logic, energy saving potential and optimum operating frequency, are investigated, as well as degradation related issues. Adiabatic logic benefits from future devices, is not susceptible to Hot Carrier Injection, and shows less impact of Bias Temperature Instability than static CMOS circuits. Major interest also lies on the efficient generation of the applied power-clock signal. This oscillating power supply can be used to save energy in short idle times by disconnecting circuits. An efficient way to generate the power-clock is by means of the synchronous 2N2P LC oscillator, which is also robust with respect to pattern-induced capacitive variations. An easy to implement but powerful power-clock gating supplement is proposed by gating the synchronization signals. Diverse implementations to shut down the system are presented and rated for their applicability and other aspects like energy reduction capability and data retention. Advantageous usage of adiabatic logic requires compact and efficient arithmetic structures. A broad variety of adder structures and a Coordinate Rotation Digital Computer are compared and rated according to energy consumption and area usage, and the resulting energy saving potential against static CMOS proves the ultra-low-power capability of adiabatic logic. In the end, a new circuit topology has to compete with static CMOS also in productivity. On a 130nm test chip, a large scale test vehicle containing an FIR filter was implemented in adiabatic logic, utilizing a standard, library-based design flow, fabricated, measured and compared to simulations of a static CMOS counterpart, with measured saving factors compliant to the values gained by simulation. This leads to the conclusion that adiabatic logic is ready for productive design due to compatibility not only to CMOS technology, but also to electronic design automation (EDA) tools developed for static CMOS system design.

This book presents models and procedures to design pipeline analog-to-digital converters, compensating for device inaccuracies, so that high-performance specs can be met within short design cycles. These models are capable of capturing and predicting the behavior of pipeline data converters within less than half-a-bit deviation, versus transistor-level simulations. As a result, far fewer model iterations are required across the design cycle. Models described in this book accurately predict transient behaviors, which are key to the performance of discrete-time systems and hence to the performance of pipeline data converters.

In recent years, III-V devices, integrated circuits, and superconducting integrated circuits have emerged as leading contenders for high-frequency and ultrahigh speed applications. GaAs MESFETs have been applied in microwave systems as low-noise and high-power amplifiers since the early 1970s, replacing silicon devices. The heterojunction high-electron-mobility transistor (HEMT), invented in 1980, has become a key component for satellite broadcasting receiver systems, serving as the ultra-low-noise device at 12 GHz. Furthermore, the heterojunction bipolar transistor (HBT) has been considered as having the highest switching speed and cutoff frequency in the semiconductor device field. Initially most of these devices were used for analog high-frequency applications, but there is also a strong need to develop high-speed III-V digital devices for computer, telecom munication, and instrumentation systems, to replace silicon high-speed devices, because of the switching-speed and power-dissipation limitations of silicon. The potential high speed and low power dissipation of digital integrated circuits using GaAs MESFET, HEMT, HBT, and superconducting Josephson junction devices has evoked tremendous competition in the race to develop such technology. A technology review shows that Japanese research institutes and companies have taken the lead in the development of these devices, and some integrated circuits have already been applied to supercomputers in Japan. The activities of Japanese research institutes and companies in the III-V and superconducting device fields have been superior for three reasons. First, bulk crystal growth, epitaxial growth, process, and design technology were developed at the same time."

In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes. Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that there are no manufacturing defects in the integrated circuit. It should be noted that all the above verification mechanisms deal not only with verifying the functionality of the integrated circuit but also its performance."

Predictive Technology Model for Robust Nanoelectronic Design" explains many of the technical mysteries behind the Predictive Technology Model (PTM) that has been adopted worldwide in explorative design research. Through physical derivation and technology extrapolation, PTM is the de-factor device model used in electronic design. This work explains the systematic model development and provides a guide to robust design practice in the presence of variability and reliability issues. Having interacted with multiple leading semiconductor companies and university research teams, the author brings a state-of-the-art perspective on technology scaling to this work and shares insights gained in the practices of device modeling.

Emphasizes IC design concepts with additional support for discrete design where necessary. Describes noise sources and models; addresses practical problems of circuit design for low noise using negative feedback, filtering, component noise, measurement techniques and instrumentation; gives numerous examples of practical amplifier designs. Five chapters cover the use of SPICE and PSpice for low noise analysis and design.

This book focuses on increasing the energy-efficiency of electronic devices so that portable applications can have a longer stand-alone time on the same battery. The authors explain the energy-efficiency benefits that ultra-low-voltage circuits provide and provide answers to tackle the challenges which ultra-low-voltage operation poses. An innovative design methodology is presented, verified, and validated by four prototypes in advanced CMOS technologies. These prototypes are shown to achieve high energy-efficiency through their successful functionality at ultra-low supply voltages.

This course-based text revisits classic concepts in nonlinear circuit theory from a very much introductory point of view: the presentation is completely self-contained and does not assume any prior knowledge of circuit theory. It is simply assumed that readers have taken a first-year undergraduate course in differential and integral calculus, along with an elementary physics course in classical mechanics and electrodynamics. Further, it discusses topics not typically found in standard textbooks, such as nonlinear operational amplifier circuits, nonlinear chaotic circuits and memristor networks. Each chapter includes a set of illustrative and worked examples, along with end-of-chapter exercises and lab exercises using the QUCS open-source circuit simulator. Solutions and other material are provided on the YouTube channel created for this book by the authors.

This textbook is written for junior/senior undergraduate and first-year graduate students in the electrical and computer engineering departments.

Using PSoC mixed-signal array design, the authors define the characteristics of embedd design, embedded mixed-signal architectures, and top-down design. Optimized implementations of these designs are included to illustrate the theory. Exercises are provided at the end of each chapter for practice. Topics covered include the hardware and software used to implement analog and digital interfaces, various filter structures, amplifiers and other signal-conditioning circuits, pulse-width modulators, timers, and data structures for handling multiple similar peripheral devices.

The practical exercises contained in the companion laboratory manual, which was co-authored by Cypress Staff Applications Engineer Dave Van Ess, are also based on PSoC. PSoC's integrated microcontroller, highly configurable analog/digital peripherals, and a full set of development tools make it an ideal learning tool for developing mixed-signal embedded design skills.

3. 2 Input Encoding Targeting Two-Level Logic . . . . . . . . 27 3. 2. 1 One-Hot Coding and Multiple-Valued Minimization 28 3. 2. 2 Input Constraints and Face Embedding 30 3. 3 Satisfying Encoding Constraints . . . . . . . 32 3. 3. 1 Definitions . . . . . . . . . . . . . . . 32 3. 3. 2 Column-Based Constraint Satisfaction 33 3. 3. 3 Row-Based Constraint Satisfaction . . 37 3. 3. 4 Constraint Satisfaction Using Dichotomies . 38 3. 3. 5 Simulated Annealing for Constraint Satisfaction 41 3. 4 Input Encoding Targeting Multilevel Logic. . 43 3. 4. 1 Kernels and Kernel Intersections . . . 44 3. 4. 2 Kernels and Multiple-Valued Variables 46 3. 4. 3 Multiple-Valued Factorization. . . . . 48 3. 4. 4 Size Estimation in Algebraic Decomposition . 53 3. 4. 5 The Encoding Step . 54 3. 5 Conclusion . . . . . . . . . 55 4 Encoding of Symbolic Outputs 57 4. 1 Heuristic Output Encoding Targeting Two-Level Logic. 59 4. 1. 1 Dominance Relations. . . . . . . . . . . . . . . . 59 4. 1. 2 Output Encoding by the Derivation of Dominance Relations . . . . . . . . . . . . . . . . . . . . . 60 . . 4. 1. 3 Heuristics to Minimize the Number of Encoding Bits . . . . . . . . . . . . 64 4. 1. 4 Disjunctive Relationships . . . . . . . . . . . 65 4. 1. 5 Summary . . . . . . . . . . . . . . . . . . 66 . . 4. 2 Exact Output Encoding Targeting Two-Level Logic. 66 4. 2. 1 Generation of Generalized Prime Implicants . 68 4. 2. 2 Selecting a Minimum Encodeable Cover . . . 68 4. 2. 3 Dominance and Disjunctive Relationships to S- isfy Constraints . . . . . . . . . . . 70 4. 2. 4 Constructing the Optimized Cover 73 4. 2. 5 Correctness of the Procedure . . 73 4. 2. 6 Multiple Symbolic Outputs . . .

This book describes a circuit architecture for converting real analog signals into a digital format, suitable for digital signal processors. This architecture, referred to as multi-stage noise-shaping (MASH) Continuous-Time Sigma-Delta Modulators (CT- M), has the potential to provide better digital data quality and achieve better data rate conversion with lower power consumption. The authors not only cover MASH continuous-time sigma delta modulator fundamentals, but also provide a literature review that will allow students, professors, and professionals to catch up on the latest developments in related technology.

Current books on low voltage analog design typically cover techniques for supply voltages down to approximately 1V. This book presents novel ideas and results for operation from much lower supply voltages and the techniques presented are basic circuit techniques that are widely applicable beyond the scope of the presented examples. Analog Circuit Design Techniques at 0.5V is written for analog circuit designers and researchers as well as graduate students studying semiconductors and integrated circuit design.

Logic design of digital devices is a very important part of the Computer Science. It deals with design and testing of logic circuits for both data-path and control unit of a digital system. Design methods depend strongly on logic elements using for implementation of logic circuits. Different programmable logic devices are wide used for implementation of logic circuits. Nowadays, we witness the rapid growth of new and new chips, but there is a strong lack of new design methods.

This book includes a variety of design and test methods targeted on different digital devices. It covers methods of digital system design, the development of theoretical base for construction and designing of the PLD-based devices, application of UML for digital design. A considerable part of the book is devoted to design methods oriented on implementing control units using FPGA and CPLD chips. Such important issues as design of reliable FSMs, automatic design of concurrent logic controllers, the models and methods for creating infrastructure IP services for the SoCs are also presented.

The editors of the book hope that it will be interesting and useful for experts in Computer Science and Electronics, as well as for students, who are viewed as designers of future digital devices and systems.