One of the keys to success in the IC industry is getting a new product to market in a timely fashion and being able to produce that product with sufficient yield to be profitable. There are two ways to increase yield: by improving the control of the manufacturing process and by designing the process and the circuits in such a way as to minimize the effect of the inherent variations of the process on performance. The latter is typically referred to as "design for manufacture" or "statistical design." As device sizes continue to shrink, the effects of the inherent fluctuations in the IC fabrication process will have an even more obvious effect on circuit performance. And design for manufacture will increase in importance. We have been working in the area of statistically based computer aided design for more than 13 years. During the last decade we have been working with each other, and individually with our students, to develop methods and CAD tools that can be used to improve yield during the design and manufacturing phases of IC realization. This effort has resulted in a large number of publications that have appeared in a variety of journals and conference proceedings. Thus our motivation in writing this book is to put, in one place, a description of our approach to IC yield enhancement. While the work that is contained in this book has appeared in the open literature, we have attempted to use a consistent notation throughout this book.

The Integrated Circuit (IC) industry has gone without a standardized verification approach for decades. This book defines a uniform, standardizable methodology for verifying the logical behavior of an integrated circuit, whether an I/O controller, a microprocessor, or a complete digital system. This book will help Engineers and managers responsible for IC development to bring a single, standards-based methodology to their R & D efforts, cutting costs and improving results.

For real-time systems, the worst-case execution time (WCET) is the key objective to be considered. Traditionally, code for real-time systems is generated without taking this objective into account and the WCET is computed only after code generation. Worst-Case Execution Time Aware Compilation Techniques for Real-Time Systems presents the first comprehensive approach integrating WCET considerations into the code generation process. Based on the proposed reconciliation between a compiler and a timing analyzer, a wide range of novel optimization techniques is provided. Among others, the techniques cover source code and assembly level optimizations, exploit machine learning techniques and address the design of modern systems that have to meet multiple objectives.

Using these optimizations, the WCET of real-time applications can be reduced by about 30% to 45% on the average. This opens opportunities for decreasing clock speeds, costs and energy consumption of embedded processors. The proposed techniques can be used for all types real-time systems, including automotive and avionics IT systems.

Modern consumers carry many electronic devices, like a mobile phone, digital camera, GPS, PDA and an MP3 player. The functionality of each of these devices has gone through an important evolution over recent years, with a steep increase in both the number of features as in the quality of the services that they provide. However, providing the required compute power to support (an uncompromised combination of) all this functionality is highly non-trivial. Designing processors that meet the demanding requirements of future mobile devices requires the optimization of the embedded system in general and of the embedded processors in particular, as they should strike the correct balance between flexibility, energy efficiency and performance. In general, a designer will try to minimize the energy consumption (as far as needed) for a given performance, with a sufficient flexibility. However, achieving this goal is already complex when looking at the processor in isolation, but, in reality, the processor is a single component in a more complex system. In order to design such complex system successfully, critical decisions during the design of each individual component should take into account effect on the other parts, with a clear goal to move to a global Pareto optimum in the complete multi-dimensional exploration space.

In the complex, global design of battery-operated embedded systems, the focus of Ultra-Low Energy Domain-Specific Instruction-Set Processors is on the energy-aware architecture exploration of domain-specific instruction-set processors and the co-optimization of the datapath architecture, foreground memory, and instruction memory organisation with a link to the required mapping techniques or compiler steps at the early stages of the design. By performing an extensive energy breakdown experiment for a complete embedded platform, both energy and performance bottlenecks have been identified, together with the important relations between the different components. Based on this knowledge, architecture extensions are proposed for all the bottlenecks.

This book covers essential topics in the architecture and design of Internet of Things (IoT) systems. The authors provide state-of-the-art information that enables readers to design systems that balance functionality, bandwidth, and power consumption, while providing secure and safe operation in the face of a wide range of threat and fault models. Coverage includes essential topics in system modeling, edge/cloud architectures, and security and safety, including cyberphysical systems and industrial control systems.

This title introduces state-of-the-art design principles for SOI circuit design, and is primarily concerned with circuit-related issues. It considers SOI material in terms of implementation that is promising or has been used elsewhere in circuit development, with historical perspective where appropriate.

Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results.
The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.

Environmental electromagnetic pollution has drastically increased over the last decades. The omnipresence of communication systems, various electronic appliances and the use of ever increasing frequencies, all contribute to a noisy electromagnetic environment which acts detrimentally on sensitive electronic equipment. Integrated circuits must be able to operate satisfactorily while cohabiting harmoniously in the same appliance, and not generate intolerable levels of electromagnetic emission, while maintaining a sound immunity to potential electromagnetic disturbances: analog integrated circuits are in particular more easily disturbed than their digital counterparts, since they don't have the benefit of dealing with predefined levels ensuring an innate immunity to disturbances. The objective of the research domain presented in EMC of Analog Integrated Circuits is to improve the electromagnetic immunity of considered analog integrated circuits, so that they start to fail at relevantly higher conduction levels than before.

"There are three words that characterize this work: thoroughness, completeness and clarity. The authors are congratulated for taking the time to write an excellent linear systems textbook! a ]The authors have used their mastery of the subject to produce a textbook that very effectively presents the theory of linear systems as it has evolved over the last thirty years. The result is a comprehensive, complete and clear exposition that serves as an excellent foundation for more advanced topics in system theory and control." a "IEEE Transactions on Automatic Control

"In assessing the present book as a potential textbook for our first graduate linear systems course, I find...[that] Antsaklis and Michel have contributed an expertly written and high quality textbook to the field and are to be congratulateda ]. Because of its mathematical sophistication and completeness the present book is highly recommended for use, both as a textbook as well as a reference." a "Automatica

Linear systems theory plays a broad and fundamental role in electrical, mechanical, chemical and aerospace engineering, communications, and signal processing. A thorough introduction to systems theory with emphasis on control is presented in this self-contained textbook.

The book examines the fundamental properties that govern the behavior of systems by developing their mathematical descriptions. Linear time-invariant, time-varying, continuous-time, and discrete-time systems are covered. Rigorous development of classic and contemporary topics in linear systems, as well as extensive coverage of stability and polynomial matrix/fractional representation, provide the necessary foundation for further study of systemsand control.

Linear Systems is written as a textbook for a challenging one-semester graduate course; a solutions manual is available to instructors upon adoption of the text. The booka (TM)s flexible coverage and self-contained presentation also make it an excellent reference guide or self-study manual.

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For a treatment of linear systems that focuses primarily on the time-invariant case using streamlined presentation of the material with less formal and more intuitive proofs, see the authorsa (TM) companion book entitled A Linear Systems Primer.

This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary "User Constraints File". The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from user-level specifications. This tool has been used to implement the proposed circuits, as well as hardware implementations of integer arithmetic algorithms where several of the proposed circuits are used as building blocks. Implementation results demonstrate higher performance and superior operand-width scalability for the proposed circuits, with respect to implementations derived through other existing approaches. This book will prove useful to researchers, students and professionals engaged in the domain of FPGA circuit optimization and implementation.

Recently there has been increased interest in the development of computer-aided design programs to support the system level designer of integrated circuits more actively. Such design tools hold the promise of raising the level of abstraction at which an integrated circuit is designed, thus releasing the current designers from many of the details of logic and circuit level design. The promise further suggests that a whole new group of designers in neighboring engineering and science disciplines, with far less understanding of integrated circuit design, will also be able to increase their productivity and the functionality of the systems they design. This promise has been made repeatedly as each new higher level of computer-aided design tool is introduced and has repeatedly fallen short of fulfillment. This book presents the results of research aimed at introducing yet higher levels of design tools that will inch the integrated circuit design community closer to the fulfillment of that promise. 1. 1. SYNTHESIS OF INTEGRATED CmCUITS In the integrated circuit (Ie) design process, a behavior that meets certain specifications is conceived for a system, the behavior is used to produce a design in terms of a set of structural logic elements, and these logic elements are mapped onto physical units. The design process is impacted by a set of constraints as well as technological information (i. e. the logic elements and physical units used for the design).

Micro-electronics and so integrated circuit design are heavily driven by technology scaling. The main engine of scaling is an increased system performance at reduced manufacturing cost (per system). In most systems digital circuits dominate with respect to die area and functional complexity. Digital building blocks take full - vantage of reduced device geometries in terms of area, power per functionality, and switching speed. On the other hand, analog circuits rely not on the fast transition speed between a few discrete states but fairly on the actual shape of the trans- tor characteristic. Technology scaling continuously degrades these characteristics with respect to analog performance parameters like output resistance or intrinsic gain. Below the 100 nm technology node the design of analog and mixed-signal circuits becomes perceptibly more dif cult. This is particularly true for low supply voltages near to 1V or below. The result is not only an increased design effort but also a growing power consumption. The area shrinks considerably less than p- dicted by the digital scaling factor. Obviously, both effects are contradictory to the original goal of scaling. However, digital circuits become faster, smaller, and less power hungry. The fast switching transitions reduce the susceptibility to noise, e. g. icker noise in the transistors. There are also a few drawbacks like the generation of power supply noise or the lack of power supply rejection.

This book will describe ultra low-power, integrated circuits and systems designed for the emerging field of neural signal recording and processing, and wireless communication. Since neural interfaces are typically implanted, their operation is highly energy-constrained. This book introduces concepts and theory that allow circuit operation approaching the fundamental limits. Design examples and measurements of real systems are provided. The book will describe circuit designs for all of the critical components of a neural recording system, including: Amplifiers which utilize new techniques to improve the trade-off between good noise performance and low power consumption. Analog and mixed-signal circuits which implement signal processing tasks specific to the neural recording application: Detection of neural spikes Extraction of features that describe the spikes Clustering, a machine learning technique for sorting spikes Weak-inversion operation of analog-domain transistors, allowing processing circuits that reduce the requirements for analog-digital conversion and allow low system-level power consumption. Highly-integrated, sub-mW wireless transmitter designed for the Medical Implant Communications Service (MICS) and ISM bands.

Radio-Frequency Microelectronic Circuits for Telecommunication Applications covers the design issues of radio-frequency microelectronic circuits for telecommunication applications with emphasis on devices and circuit-level design. It uses a large number of real examples from industrial design as a vehicle both to teach the principles and to ensure relevance starting from device level modeling to basic RF microelectronic circuit cell design. Modeling for high-frequency operation of both active and passive integrated devices is covered starting from the bipolar transistor to the MOS transistor to the modeling of integrated spiral inductors, resistors, capacitors, varactors and package parasitics structures. A chapter is also devoted to the presentation of the basic definitions and terminology used in RF IC design. The book continues with the presentation of the principal building blocks of an integrated RF front-end, namely, the LNA, the mixer, the VCO and integrated filters. Design paradigms are provided classified on the technology used in each case: pure bipolar, CMOS, BiCMOS or SiGe. Radio-Frequency Microelectronic Circuits for Telecommunication Applications is essential reading for all researchers, practising engineers and designers working in RF electronics. It is also a reference for use in advanced undergraduate or graduate courses in the same field.

This book is a collection of papers presented by renowned researchers, keynote speakers, and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals & Systems and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17 19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers, and academicians as well as industry professionals.

Design technology to address the new and vast problem of heterogeneous embedded systems design while remaining compatible with standard "More Moore" flows, i.e. capable of simultaneously handling both silicon complexity and system complexity, represents one of the most important challenges facing the semiconductor industry today and will be for several years to come. While the micro-electronics industry, over the years and with its spectacular and unique evolution, has built its own specific design methods to focus mainly on the management of complexity through the establishment of abstraction levels, the emergence of device heterogeneity requires new approaches enabling the satisfactory design of physically heterogeneous embedded systems for the widespread deployment of such systems.

Heterogeneous Embedded Systems, compiled largely from a set of contributions from participants of past editions of the Winter School on Heterogeneous Embedded Systems Design Technology (FETCH), proposes a necessarily broad and holistic overview of design techniques used to tackle the various facets of heterogeneity in terms of technology and opportunities at the physical level, signal representations and different abstraction levels, architectures and components based on hardware and software, in all the main phases of design (modeling, validation with multiple models of computation, synthesis and optimization). It concentrates on the specific issues at the interfaces, and is divided into two main parts. The first part examines mainly theoretical issues and focuses on the modeling, validation and design techniques themselves. The second part illustrates the use of these methods in various design contexts at the forefront of new technology and architectural developments.

This book presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. It describes state-of-the-art techniques for reducing area requirements in FPGA architectures, which also increase performance and enable reduction in power required. Coverage focuses on reduction of FPGA area by introducing heterogeneous hard-blocks (such as multipliers, adders etc) in FPGAs, and by designing application specific FPGAs. Automatic FPGA layout generation techniques are employed to decrease non-recurring engineering (NRE) costs and time-to-market of application-specific, heterogeneous FPGA architectures.

This book describes ultra low power capacitive sensor interfaces, and presents the realization of a very low power generic sensor interface chip that is adaptable to a broad range of capacitive sensors. The book opens by reviewing important design aspects for autonomous sensor systems, discusses different building blocks, and presents the modular architecture for the generic sensor interface chip. Finally, the generic sensor interface chip is shown in state-of-the-art applications.

In three main divisions the book covers combinational circuits, latches, and asynchronous sequential circuits. Combinational circuits have no memorising ability, while sequential circuits have such an ability to various degrees. Latches are the simplest sequential circuits, ones with the shortest memory. The presentation is decidedly non-standard. The design of combinational circuits is discussed in an orthodox manner using normal forms and in an unorthodox manner using set-theoretical evaluation formulas relying heavily on Karnaugh maps. The latter approach allows for a new design technique called composition. Latches are covered very extensively. Their memory functions are expressed mathematically in a time-independent manner allowing the use of (normal, non-temporal) Boolean logic in their calculation. The theory of latches is then used as the basis for calculating asynchronous circuits. Asynchronous circuits are specified in a tree-representation, each internal node of the tree representing an internal latch of the circuit, the latches specified by the tree itself. The tree specification allows solutions of formidable problems such as algorithmic state assignment, finding equivalent states non-recursively, and verifying asynchronous circuits.

This reference is for anyone involved with microwave design. It tackles the practical aspects of microwave statistical design and introduces statistical design techniques that encompass many different applications. This presentation focuses on two main example areas - microwave circuits and systems - but any application with a complex relation between design variables and performance and design variable uncertainty can benefit from statistical design.

A silicon compiler is a software system which can automatically generate an integrated circuit from a user's specification. Anatomy of a Silicon Compiler examines one such compiler in detail, covering the basic framework and design entry, the actual algorithms and libraries which are used, the approach to verification and testing, behavioral synthesis tools and several applications which demonstrate the system's capabilities.

It is a great honor to provide an introduction for Dr. Frank Op 't Eynde's and Dr. Willy Sansen's book "Analog Interfaces for Digital Signal Processing Systems." The field of analog integrated circuit design is undergoing rapid evolution. The pervasiveness of digital processing has considerably modified the micro-system architectures: the analog part of complex mixed systems is more and more pushed at the boundary limits of the processing chain. Moreover, the increased performance of digital circuits, in terms of accuracy and speed, are making the specification requirements of analog circuits very strict. In addition to this, the technology, supply voltage and power consumption of analog circuits must be compatible with those, typical for digital circuits. Therefore, in a few words, analog circuits are becoming complex and specialised interfaces between the real world and digital signal processing domains. This technological evolution should be accompanied by an equivalently fast evolution in designer competencies. Knowledge of complicated signal handling should be quickly replaced by know-how of simple but very accurate and very fast signal processing and a solid background in data conversion techniques. All of this through the use of the CMOS (and possibly BiCMOS) technology.

Analog Circuit Design contains the contribution of 18 tutorials of the 20th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 20 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of:
Topic 1: Low Voltage Low Power, chairman: Andrea Baschirotto
Topic 2: Short Range Wireless Front-Ends, chairman: Arthur van Roermund
Topic 3: Power Management and DC-DC, chairman: Michiel Steyaert.
Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design course.