Systematic Design of Sigma-Delta Analog-to-Digital Converters describes the issues related to the sigma-delta analog-to-digital converters (ADCs) design in a systematic manner: from the top level of abstraction represented by the filters defining signal and noise transfer functions (STF, NTF), passing through the architecture level where topology-related performance is calculated and simulated, and finally down to parameters of circuit elements like resistors, capacitors, and amplifier transconductances used in individual integrators. The systematic approach allows the evaluation of different loop filters (order, aggressiveness, discrete-time or continuous-time implementation) with quantizers varying in resolution. Topologies explored range from simple single loops to multiple cascaded loops with complex structures including more feedbacks and feedforwards. For differential circuits, with switched-capacitor integrators for discrete-time (DT) loop filters and active-RC for continuous-time (CT) ones, the passive integrator components are calculated and the power consumption is estimated, based on top-level requirements like harmonic distortion and noise budget.
This unified, systematic approach to choosing the best sigma-delta ADC implementation for a given design target yields an interesting solution for a high-resolution, broadband (DSL-like) ADC operated at low oversampling ratio, which is detailed down to transistor-level schematics.
The target audience of Systematic Design of Sigma-Delta Analog-to-Digital Converters are engineers designing sigma-delta ADCs and/or switched-capacitor and continuous-time filters, both beginners and experienced. It is also intended forstudents/academics involved in sigma-delta and analog CAD research.

The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solutions follows a similar approach. This is an area of processor design that is still in its early stages of exploration and that holds the promise of accomplishing the ultimate goal of achieving complete correctness guarantees for microprocessor-based computation. The authors conclude the book with a look towards the future of late-stage verification and its growing role in the processor life-cycle.

CMOS Memory Circuits is a systematic and comprehensive reference work designed to aid in the understanding of CMOS memory circuits, architectures, and design techniques. CMOS technology is the dominant fabrication method and almost the exclusive choice for semiconductor memory designers. Both the quantity and the variety of complementary-metal-oxide-semiconductor (CMOS) memories are staggering. CMOS memories are traded as mass-products worldwide and are diversified to satisfy nearly all practical requirements in operational speed, power, size, and environmental tolerance. Without the outstanding speed, power, and packing density characteristics of CMOS memories, neither personal computing, nor space exploration, nor superior defense systems, nor many other feats of human ingenuity could be accomplished. Electronic systems need continuous improvements in speed performance, power consumption, packing density, size, weight, and costs. These needs continue to spur the rapid advancement of CMOS memory processing and circuit technologies. CMOS Memory Circuits is essential for those who intend to (1) understand, (2) apply, (3) design and (4) develop CMOS memories.

With the development of Very-Deep Sub-Micron technologies, process variability is becoming increasingly important and is a very important issue in the design of complex circuits. Process variability is the statistical variation of process parameters, meaning that these parameters do not have always the same value, but become a random variable, with a given mean value and standard deviation. This effect can lead to several issues in digital circuit design.

The logical consequence of this parameter variation is that circuit characteristics, as delay and power, also become random variables. Because of the delay variability, not all circuits will now have the same performance, but some will be faster and some slower. However, the slowest circuits may be so slow that they will not be appropriate for sale. On the other hand, the fastest circuits that could be sold for a higher price can be very leaky, and also not very appropriate for sale. A main consequence of power variability is that the power consumption of some circuits will be different than expected, reducing reliability, average life expectancy and warranty of products. Sometimes the circuits will not work at all, due to reasons associated with process variations. At the end, these effects result in lower yield and lower profitability.

To understand these effects, it is necessary to study the consequences of variability in several aspects of circuit design, like logic gates, storage elements, clock distribution, and any other that can be affected by process variations. The main focus of this book will be storage elements.

Enables the reader to test an analog circuit that is implemented either in bipolar or MOS technology.

Examines the testing and fault diagnosis of analog and analog part of mixed signal circuits.

Covers the testing and fault diagnosis of both bipolar and Metal Oxide Semiconductor (MOS) circuits and introduces .

Also contains problems that can be used as quiz or homework.

This comprehensive and insightful book discusses ESD protection circuit design problems from an IC designer's perspective. On-Chip ESD Protection for Integrated Circuits: An IC Design Perspective provides both fundamental and advanced materials needed by a circuit designer for designing ESD protection circuits, including:

• Testing models and standards adopted by U.S. Department of Defense, EIA/JEDEC, ESD Association, Automotive Electronics Council, International Electrotechnical Commission, etc.
• ESD failure analysis, protection devices, and protection of sub-circuits
• Whole-chip ESD protection and ESD-to-circuit interactions
• Advanced low-parasitic compact ESD protection structures for RF and mixed-signal IC's
• Mixed-mode ESD simulation-design methodologies for design prediction ESD-to-circuit interactions, and more!

The interest for :I:~ modulation-based NO converters has significantly increased in the last years. The reason for that is twofold. On the one hand, unlike other converters that need accurate building blocks to obtain high res olution, :I:~ converters show low sensitivity to the imperfections of their building blocks. This is achieved through extensive use of digital signal pro cessing - a desirable feature regarding the implementation of NO interfaces in mainstream CMOS technologies which are better suited for implementing fast, dense, digital circuits than accurate analog circuits. On the other hand, the number of applications with industrial interest has also grown. In fact, starting from the earliest in the audio band, today we can find :I:~ converters in a large variety of NO interfaces, ranging from instrumentation to commu nications. These advances have been supported by a number of research works that have lead to a considerably large amount of published papers and books cov ering different sub-topics: from purely theoretical aspects to architecture and circuit optimization. However, so much material is often difficultly digested by those unexperienced designers who have been committed to developing a :I:~ converter, mainly because there is a lack of methodology. In our view, a clear methodology is necessary in :I:~ modulator design because all related tasks are rather hard.

Although exploratory and developmental activity in electron beam testing (EBT) 25 years, it was not had already been in existence in research laboratories for over until the beginning of the 1980s that it was taken up seriously as a technique for integrated circuit (IC) testing. While ICs were being fabricated on design rules of several microns, the mechanical ne edle probe served quite adequately for internal chip probing. This scenario changed with growing device complexity and shrinking geometries, prompting IC manufacturers to take note ofthis new testing technology. It required several more years and considerable investment by electron beam tester manufacturers, however, to co me up with user-friendly automated systems that were acceptable to IC test engineers. These intervening years witnessed intense activity in the development of instrumentation, testing techniques, and system automation, as evidenced by the proliferation of technical papers presented at conferences. With the shift of interest toward applications, the technology may now be considered as having come of age.

From the reviews: ..". this is a well produced book, written in a easy to read style, and will also be a very useful primer for someone starting out the field ...], and a useful source of reference for experienced users ..." Microelectronics Journal

Modeling of Induction Motors with One and Two Degrees of Mechanical Freedom will be of interest to electrical engineering academics and graduate students as well as electric machine designers and engineers involved in control, mechatronics, and automation.
This book presents the mathematical model of induction motors with two degrees of mechanical freedom (IM-2DMF), formed in the electromagnetic field as well as in circuit theory, which allows analyzing the performance of these three groups of motors taking into account edge effects, winding and current asymmetry. The model derived is based on the concept of magnetic field wave moving in the air-gap with a helical motion. In general, the rotor moves helically too with the rotary-linear slip. The electromagnetic field as well as motor performance of the particular motors is analyzed.
The mathematical model of IM-2DMF is more general to the model of induction motors with one degree of mechanical freedom, i.e. rotary and linear motors. Examples of modeling two types of rotary disc motors and flat linear motor with twisted primary part are presented with inclusion of finite stator and rotor length and width effects. The simulation results are backed by the measurements carried out on the laboratory models, which were tested on the unique measurement stand.
By presenting the theory of a group of induction motors with two degrees of mechanical freedom and giving a basis for designing of these type of motors, as well as to give the tool for analysis of their performance, Modeling of Induction Motors with One and Two Degrees of Mechanical Freedom is a must-have book for electrical engineering graduate students and electric machine designers and engineers.

This book discusses various aspects, challenges, and solutions for developing systems-of-systems for situation awareness, using applications in the domain of maritime safety and security. Topics include advanced, multi-objective visualization methods for situation awareness, stochastic outlier selection, rule-based anomaly detection, an ontology-based event model for semantic reasoning, new methods for semi-automatic generation of adapters bridging communication gaps, security policies for systems-of-systems, trust assessment, and methods to deal with the dynamics of systems-of-systems in run-time monitoring, testing, and diagnosis. Architectural considerations for designing information-centric systems-of-systems such as situation awareness systems, and an integrated demonstrator implementing many of the investigated aspects, complete the book.

High-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters as follows. Chapter 1 provides an overview to the design of clock networks. Chapter 2 specifies the timing requirements in digital design. Chapter 3 shows the circuits of sequential elements including latches and flip-flops. Chapter 4 describes the domino circuits, which need special clock signals. Chapter 5 discusses the phase-locked loop (PLL) and delay-locked loop (DLL), which provide the clock generation and de-skewing for the on-chip clock distribution. Chapter 6 summarizes the clock distribution techniques published in the state-of-the-art microprocessor chips. Chapter 7 describes the CAD flow on the clock network simulation. Chapter 8 gives the research work on low-voltage swing clock distribution. Chapter 9 explores the possibility of placing the global clock tree on the package layers. Chapter 10 shows the algorithms of balanced clock routing and wire sizing for the skew minimization. Chapter 11 shows a commercial CAD tool that deals with clock tree synthesis in the ASIC design flow. The glossary is attached at the end of this book. The clock network design is still a challenging task in most high-speed VLSI chips, since the clock frequency and power consumption requirements are increasingly difficult to meet for multiple clock networks on the chip. Many research works and industry examples will be shown in this area to continually improve the clock distribution networks for future high-performance chips.

Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering.

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.

It is a great honor to provide a few words of introduction for Dr. Georges Gielen's and Prof. Willy Sansen's book "Symbolic analysis for automated design of analog integrated circuits." The symbolic analysis method presented in this book represents a significant step forward in the area of analog circuit design. As demonstrated in this book, symbolic analysis opens up new possibilities for the development of computer-aided design (CAD) tools that can analyze an analog circuit topology and automatically size the components for a given set of specifications. Symbolic analysis even has the potential to improve the training of young analog circuit designers and to guide more experienced designers through second-order phenomena such as distortion. This book can also serve as an excellent reference for researchers in the analog circuit design area and creators of CAD tools, as it provides a comprehensive overview and comparison of various approaches for analog circuit design automation and an extensive bibliography. The world is essentially analog in nature, hence most electronic systems involve both analog and digital circuitry. As the number of transistors that can be integrated on a single integrated circuit (IC) substrate steadily increases over time, an ever increasing number of systems will be implemented with one, or a few, very complex ICs because of their lower production costs.

Feedback-Based Orthogonal Digital Filters: Theory, Applications, and Implementation develops the theory of a feedback-based orthogonal digital filter and examines several applications where the filter topology leads to a simple and efficient solution. The development of the filter structure is linked to concepts in observer theory. Several signal processing problems can be represented as estimation problems, where a parametric representation of the input is used, to try and replicate it locally. This estimation problem can be solved using an identity observer, and the filter topology falls in this framework. Hence the filter topology represents a universal building block that can find application in several problems, such as spectral estimation, time-recursive computation of transforms, etc. Further, because of the orthogonality constraints satisfied by the structure, it also represents a robust solution under finite precision conditions. The book also presents the observer-based viewpoint of several signal processing problems, and shows that problems that are typically treated independently in the literature are in fact linked and can be cast in a single unified framework. In addition to examining the theoretical issues, the book describes practical issues related to a hardware implementation of the building block, in both the digital and analog domain. On the digital side, issues relating to implementation using semi-custom chips (FPGA's), and ASIC design are examined. On the analog side, the design and testing of a fabricated chip, that functions as a multi-sinusoidal phase-locked-loop, are described. Feedback-Based Orthogonal Digital Filters serves as an excellent reference. May be used as a text for advanced courses on the subject.

This book introduces a family of new methods for accurate and robust spectral testing and fills an information gap, as the requirements in standard test have grown increasingly challenging in recent high precision testing, especially as the device performance has continued to improve. Test engineers will be enabled to accurately set their devices & systems at much simpler test setup, much reduced complexity and much lower cost.

This useful monograph presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques.

This book systematically describes the design options for micro systems as well as the equations needed for calculating the behavior of their basic elements. The fundamental equations needed to calculate the effects and forces that are important in micro systems are also provided. Readers do not require previous knowledge of fabrication processes. This second edition of the volume is a thoroughly revised and extended update. The target audience primarily comprises experts in the field of micro systems and the book is also suitable for graduate engineering students. For quick reference, equations are presented in tables that can be found in an index at the end of the book.

This book focus on Long Term Evolution (LTE) and beyond. The chapters describe different aspects of research and development in LTE, LTE-Advanced (4G systems) and LTE-450 MHz such as telecommunications regulatory framework, voice over LTE, link adaptation, power control, interference mitigation mechanisms, performance evaluation for different types of antennas, cognitive mesh network, integration of LTE network and satellite, test environment, power amplifiers and so on. It is useful for researchers in the field of mobile communications.

This volume addresses the low-power low-voltage Sigma-Delta ADC design in nanometer CMOS technologies at both the circuit-level and the system level. The low-power low-voltage Sigma-Delta modulator design at the circuit level is introduced. A design example is presented in this book. This design is the first published Sigma-Delta design in a 90-nm CMOS technology and reaches a very high figure-of-merit. At the system level, a novel systematic study on the full feedforward Sigma-Delta topology is presented in this book. As a design example, a fourth-order single-loop full feedforward Sigma-Delta modulator design in a 130-nm pure digital CMOS technology is presented. This design is the first design using the full feedforward Sigma-Delta topology and reaches the highest conversion speed among all the 1-V Sigma-Delta modulators to date.

This book describes an ECG processing architecture that guides biomedical SoC developers, from theory to implementation and testing. The authors provide complete coverage of the digital circuit implementation of an ultra-low power biomedical SoC, comprised of a detailed description of an ECG processor implemented and fabricated on chip. Coverage also includes the challenges and tradeoffs of designing ECG processors. Describes digital circuit architecture for implementing ECG processing algorithms on chip; Includes coverage of signal processing techniques for ECG processing; Features ultra-low power circuit design techniques; Enables design of ECG processing architectures and their respective on-chip implementation.

This "current-amplifier cookbook" contains an extensive review of different current amplifier topologies realisable with modern CMOS integration technologies. The book derives the seldom-discussed issue of high-frequency distortion performance for all reviewed amplifier topologies, using as simple and intuitive mathematical methods as possible.

This book provides readers with a state-of-the-art description of techniques to be used for ultra-low-power (ULP) and ultra-low-cost (ULC), short-range wireless receivers. Readers will learn what is required to deploy these receivers in short-range wireless sensor networks, which are proliferating widely to serve the internet of things (IoT) for "smart cities." The authors address key challenges involved with the technology and the typical tradeoffs between ULP and ULC. Three design examples with advanced circuit techniques are described in order to address these trade-offs, which special focus on cost minimization. These three techniques enable respectively, cascading of radio frequency (RF) and baseband (BB) circuits under an ultra-low-voltage (ULV) supply, cascading of RF and BB circuits in current domain for current reuse and a novel function-reuse receiver architecture, suitable for ULV and multi-band ULP applications such as the sub-GHz ZigBee.