This book describes the trends, challenges and solutions in computing use for scientific research and development within different domains in Africa, such as health, agriculture, environment, economy, energy, education and engineering. The benefits expected are discussed by a number of recognized, domain-specific experts, with a common theme being computing as solution enabler. This book is the first document providing such a representative up-to-date view on this topic at the continent level.

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library.
Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability.
The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.
Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.

Circuit simulation is essential in integrated circuit design, and the accuracy of circuit simulation depends on the accuracy of the transistor model. BSIM3v3 (BSIM for Berkeley Short-channel IGFET Model) has been selected as the first MOSFET model for standardization by the Compact Model Council, a consortium of leading companies in semiconductor and design tools. In the next few years, many fabless and integrated semiconductor companies are expected to switch from dozens of other MOSFET models to BSIM3. This will require many device engineers and most circuit designers to learn the basics of BSIM3. MOSFET Modeling & BSIM3 User's Guide explains the detailed physical effects that are important in modeling MOSFETs, and presents the derivations of compact model expressions so that users can understand the physical meaning of the model equations and parameters. It is the first book devoted to BSIM3. It treats the BSIM3 model in detail as used in digital, analog and RF circuit design. It covers the complete set of models, i.e., I-V model, capacitance model, noise model, parasitics model, substrate current model, temperature effect model and non quasi-static model. MOSFET Modeling & BSIM3 User's Guide not only addresses the device modeling issues but also provides a user's guide to the device or circuit design engineers who use the BSIM3 model in digital/analog circuit design, RF modeling, statistical modeling, and technology prediction. This book is written for circuit designers and device engineers, as well as device scientists worldwide. It is also suitable as a reference for graduate courses and courses in circuit design or device modelling. Furthermore, it can be used as a textbook for industry courses devoted to BSIM3. MOSFET Modeling & BSIM3 User's Guide is comprehensive and practical. It is balanced between the background information and advanced discussion of BSIM3. It is helpful to experts and students alike.

This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.

This thesis introduces a successfully designed and commissioned intelligent health monitoring system, specifically for use on any industrial robot, which is able to predict the onset of faults in the joints of the geared transmissions. However the developed embedded wireless condition monitoring system leads itself very well for applications on any power transmission equipment in which the loads and speeds are not constant, and access is restricted. As such this provides significant scope for future development. Three significant achievements are presented in this thesis. First, the development of a condition monitoring algorithm based on vibration analysis of an industrial robot for fault detection and diagnosis. The combined use of a statistical control chart with time-domain signal analysis for detecting a fault via an arm-mounted wireless processor system represents the first stage of fault detection. Second, the design and development of a sophisticated embedded microprocessor base station for online implementation of the intelligent condition monitoring algorithm, and third, the implementation of a discrete wavelet transform, using an artificial neural network, with statistical feature extraction for robot fault diagnosis in which the vibration signals are first decomposed into eight levels of wavelet coefficients.

"Simulation and Verification of Electronic and Biological Systems" provides a showcase for the Circuit and Multi-Domain Simulation Workshop held in San Jose, California, USA, on November 5, 2009. The nine chapters are contributed by experts in the field and provide a broad discussion of recent developments on simulation, modeling and verification of integrated circuits and biological systems.

Specific topics include large scale parallel circuit simulation, industrial practice of fast SPICE simulation, structure-preserving model order reduction of interconnects, advanced simulation techniques for oscillator networks, dynamic stability of static memories and biological systems as well as verification of analog integrated circuits.

Simulation and verification are fundamental enablers for understanding, analyzing and designing an extremely broad range of engineering and biological circuits and systems. The design of nanometer integrated electronic systems and emerging biomedical applications have stimulated the development of novel simulation and verification techniques and methodologies. "Simulation and Verification of Electronic and Biological Systems" provides a broad discussion of recent advances on simulation, modeling and verification of integrated circuits and biological systems and offers a basis for stimulating new innovations.

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This book is far more than just another tutorial or reference guide - it's a tour through the world of analog design, combining theory and applications with the philosophies behind the design process. Readers will learn how leading analog circuit designers approach problems and how they think about solutions to those problems. They'll also learn about the analog way' - a broad, flexible method of thinking about analog design tasks.

A comprehensive and useful guide to analog theory and applications.
Covers visualizing the operation of analog circuits.
Looks at how to rapidly determine workable approximations of analog circuit parameters.

Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers. A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model. A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits. The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.

This book is a comprehensive guide to assertion-based verification of hardware designs using System Verilog Assertions (SVA). It enables readers to minimize the cost of verification by using assertion-based techniques in simulation testing, coverage collection and formal analysis. The book provides detailed descriptions of all the language features of SVA, accompanied by step-by-step examples of how to employ them to construct powerful and reusable sets of properties. The book also shows how SVA fits into the broader System Verilog language, demonstrating the ways that assertions can interact with other System Verilog components. The reader new to hardware verification will benefit from general material describing the nature of design models and behaviors, how they are exercised, and the different roles that assertions play. This second edition covers the features introduced by the recent IEEE 1800-2012. System Verilog standard, explaining in detail the new and enhanced assertion constructs. The book makes SVA usable and accessible for hardware designers, verification engineers, formal verification specialists and EDA tool developers. With numerous exercises, ranging in depth and difficulty, the book is also suitable as a text for students.

This volume emphasizes the design and development of advanced switched-opamp architectures and techniques for low-voltage low-power switched-capacitor systems. It presents a novel multi-phase switched-opamp technique together with new system architectures that are critical in improving significantly the performance of switched-capacitor systems at low supply voltages.

Asynchronous Pulse Logic is a comprehensive analysis of a newly developed asynchronous circuit family. The book covers circuit theory, practical circuits, design tools and an example of the design of a simple asynchronous microprocessor using the circuit family. Asynchronous Pulse Logic will be of interest to industrial and academic researcher working on high-speed VLSI systems. Graduate students will find this useful reference for computer-aided design of asynchronous or related VLSI systems.

Discusses process variation, model accuracy, design flow and many other practical engineering, reliability and manufacturing issues

Gives a good overview for a person who is not an expert in modeling and simulation, enabling them to extract the necessary information to competently use modeling and simulation programs

Written for engineering students and product design engineers

Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.

Evolvability, the ability to respond effectively to change, represents a major challenge to today's high-end embedded systems, such as those developed in the medical domain by Philips Healthcare. These systems are typically developed by multi-disciplinary teams, located around the world, and are in constant need of upgrading to provide new advanced features, to deal with obsolescence, and to exploit emerging enabling technologies. Despite the importance of evolvability for these types of systems, the field has received scant attention from the scientific and engineering communities.

Views on Evolvability of Embedded Systems focuses on the topic of evolvability of embedded systems from an applied scientific perspective. In particular, the book describes results from the Darwin project that researched evolvability in the context of Magnetic Resonance Imaging (MRI) systems. This project applied the Industry-as-Laboratory paradigm, in which industry and academia join forces to ensure continuous knowledge and technology transfer during the project's lifetime. The Darwin project was a collaboration between the Embedded Systems Institute, the MRI business unit of Philips Healthcare, Philips Research, and five Dutch universities.

Evolvability was addressed from a system engineering perspective by a number of researchers from different disciplines such as software-, electrical- and mechanical engineering, with a clear focus on economic decision making. The research focused on four areas: data mining, reference architectures, mechanisms and patterns for evolvability, in particular visualization & modelling, and economic decision making. Views on Evolvability of Embedded Systems is targeted at both researchers and practitioners; they will not only find a state-of-the-art overview on evolvability research, but also guidelines to make systems more evolvable and new industrially-validated techniques to improve the evolvability of embedded systems.

There is an ever increasing trend towards putting entire systems on a single chip. This means that analog circuits will have to coexist on the same substrate along with massive digital systems. Since technologies are optimized with these digital systems in mind, designers will have to make do with standard CMOS processes in the years to come. We address analog filter design from this perspective. Filters form important blocks in applications ranging from computer disc-drive chips to radio transceivers. In this book, we develop the theory and techniques necessary for the implementation of high frequency (hundreds of megahertz) programmable continuous time filters in standard CMOS processes. Since high density poly-poly capacitors are not available in these technologies, alternative capacitor structures have to be found. Met- metal capacitors have low specific capacitance. An alternative is to use the (inherently nonlinear) capacitance formed by MOSFET gates. In Chapter 2, we focus on the use of MOS capacitors as integrating elements. A physics-based model which predicts distortion accurately is presented for a two-terminal MOS structure in accumulation. Distortion in these capacitors as a function of signal swing and bias voltage is computed. Chapter 3 reviews continuous-time filter architectures in the light of bias-dependent integrating capacitors. We also discuss the merits and demerits of various CMOS transconductance elements. The problems encountered in designing high frequency programmable filters are discussed in detail.

This book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques.

This volume of Analog Circuit Design concentrates on three topics: Operational Amplifiers. A-to-D converters and Analog CAD. The book comprises six papers on each topic written by internationally recognised experts. These papers have a tutorial nature aimed at improving the design of analog circuits. The book is divided into three parts. Part I, Operational Amplifiers, presents new technologies for the design of Op-Amps in both bipolar and CMOS technologies. Two papers demonstrate techniques for improving frequency and gain behavior at high voltage. Low voltage bipolar Op-Amp design is treated in another paper. The realization high-speed and high gain VLSI building blocks in CMOS is demonstrated in two papers. The final paper shows how to provide output power with CMOS buffer amplifiers. Part II, Analog-to-Digital Conversion, presents papers which address very high conversion speeds and very high resolution implementations using sigma-delta modulation architectures. Analog to Digital converters provide the link between the analog world of transducers and the digital world of signal processing and computing. High-performance bipolar and MOS technologies result in high-resolution or high-speed convertors which can be applied in digital audio or video systems. Furthermore, the advanced high-speed bipolar technologies show an increase in conversion speed into the gigahertz range. Part III, Analog Computer Aided Design, presents the latest research towards providing analog circuit designers with the tools needed to automate much of the design process. The techniques and methodologies described demonstrate the advances being made in developing analog design tools comparable with those alreadyavailable for digital design. The papers in this volume are based on those presented at the Workshop on Advances in Analog Circuit Design held in Delft, The Netherlands in 1992. The main intention of the workshop was to brainstorm with a group of about 100 analog design experts on the new possibilities and future developments on the above topics. The result of this brainstorming is contained in Analog Circuit Design, which is thus an important reference for researchers and design engineers working in the forefront of analog circuit design and research.

A Guide to VHDL, Second Edition is intended for the working engineer who needs to develop, document, simulate, and synthesize a design using the VHDL language. It is for system and chip designers who are working with VHDL CAD tools, and who have some experience programming in Fortran, Pascal, or C and have used a logic simulator. A Guide to VHDL, Second Edition includes a number of paper exercises and computer lab experiments. If a compiler/simulator is available to the reader, then the lab exercises included in the chapters can be run to reinforce the learning experience. For practical purposes, this book keeps simulator-specific text to a minimum, but does use the Synopsys VHDL Simulator command language in a few cases. A Guide to VHDL, Second Edition is designed as a primer and its contents are appropriate for an introductory course in VHDL. The VHDL language was updated in 1992 with some minor improvements. In most cases, the language is upward compatible. Although this book is based primarily on the VHDL 1987 standard, this new second edition indicates the significant changes in the 1992 language to assist the designer in writing upwardly compatible code.

Existing sections in ESD Frim A to Z have been thoroughly revised and updated. New examples have been added to the troubleshooting chapter; and new versions of model specifications for ESD-safe handling and packaging can be found in the specifications chapter. The Appendix now includes ten recently published papers (making a total of 20) whose topics span the field of ESD control.

This book provides readers with a variety of algorithms and software tools, dedicated to the physical design of through-silicon-via (TSV) based, three-dimensional integrated circuits. It describes numerous "manufacturing-ready" GDSII-level layouts of TSV-based 3D ICs developed with the tools covered in the book. This book will also feature sign-off level analysis of timing, power, signal integrity, and thermal analysis for 3D IC designs. Full details of the related algorithms will be provided so that the readers will be able not only to grasp the core mechanics of the physical design tools, but also to be able to reproduce and improve upon the results themselves. This book will also offer various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the physical design process.

On Optimal Interconnections for VLSI describes, from a geometric perspective, algorithms for high-performance, high-density interconnections during the global and detailed routing phases of circuit layout. First, the book addresses area minimization, with a focus on near-optimal approximation algorithms for minimum-cost Steiner routing. In addition to practical implementations of recent methods, the implications of recent results on spanning tree degree bounds and the method of Zelikovsky are discussed. Second, the book addresses delay minimization, starting with a discussion of accurate, yet algorithmically tractable, delay models. Recent minimum-delay constructions are highlighted, including provably good cost-radius tradeoffs, critical-sink routing algorithms, Elmore delay-optimal routing, graph Steiner arborescences, non-tree routing, and wiresizing. Third, the book addresses skew minimization for clock routing and prescribed-delay routing formulations. The discussion starts with early matching-based constructions and goes on to treat zero-skew routing with provably minimum wirelength, as well as planar clock routing. Finally, the book concludes with a discussion of multiple (competing) objectives, i.e., how to optimize area, delay, skew, and other objectives simultaneously. These techniques are useful when the routing instance has heterogeneous resources or is highly congested, as in FPGA routing, multi-chip packaging, and very dense layouts. Throughout the book, the emphasis is on practical algorithms and a complete self-contained development. On Optimal Interconnections for VLSI will be of use to both circuit designers (CAD tool users) as well as researchers and developers in the area of performance-driven physical design.

This book describes recent findings in the domain of Boolean logic and Boolean algebra, covering application domains in circuit and system design, but also basic research in mathematics and theoretical computer science. Content includes invited chapters and a selection of the best papers presented at the 13th annual International Workshop on Boolean Problems. Provides a single-source reference to the state-of-the-art research in the field of logic synthesis and Boolean techniques; Includes a selection of the best papers presented at the 13th annual International Workshop on Boolean Problems; Covers Boolean algebras, Boolean logic, Boolean modeling, Combinatorial Search, Boolean and bitwise arithmetic, Software and tools for the solution of Boolean problems, Applications of Boolean logic and algebras, Applications to real-world problems, Boolean constraint solving, and Extensions of Boolean logic.

This book presents models and procedures to design pipeline analog-to-digital converters, compensating for device inaccuracies, so that high-performance specs can be met within short design cycles. These models are capable of capturing and predicting the behavior of pipeline data converters within less than half-a-bit deviation, versus transistor-level simulations. As a result, far fewer model iterations are required across the design cycle. Models described in this book accurately predict transient behaviors, which are key to the performance of discrete-time systems and hence to the performance of pipeline data converters.