Many dynamical systems in physics, chemistry and biology exhibit complex be haviour. The apparently random motion of a fluid is the best known example. How ever also vibrating structures, electronic oscillators, magnetic devices, lasers, chemical oscillators, and population kinetics can behave in a complicated manner. One can find irregular oscillations, which is now known as chaotic behaviour. The research field of nonlinear dynamical systems and especially the study of chaotic systems has been hailed as one of the important breaktroughs in science this century. The sim plest realization of a system with chaotic behaviour is an electronic oscillator. The purpose of this book is to provide a comprehensive introduction to the application of chaos theory to electronic systems. The book provides both the theoretical and experimental foundations of this research field. Each electronic circuit is described in detail together with its mathematical model. Controlling chaos of electronic oscilla tors is also included. End of proofs and examples are indicated by . Inside examples the end of proofs are indicated with O. We wish to express our gratitude to Catharine Thompson for a critical reading of the manuscript. Any useful suggestions and comments are welcome. Email address of the first author: MVANWYK@TSAMAIL. TRSA. AC. ZA Email address of the first author: WHS@RAU3. RAU. AC. ZA Home page of the authors: http: //zeus. rau. ac. za/steeb/steeb. html xi Chapter 1 Introduction 1."

Predictive Technology Model for Robust Nanoelectronic Design" explains many of the technical mysteries behind the Predictive Technology Model (PTM) that has been adopted worldwide in explorative design research. Through physical derivation and technology extrapolation, PTM is the de-factor device model used in electronic design. This work explains the systematic model development and provides a guide to robust design practice in the presence of variability and reliability issues. Having interacted with multiple leading semiconductor companies and university research teams, the author brings a state-of-the-art perspective on technology scaling to this work and shares insights gained in the practices of device modeling.

This volume of Analog Circuit Design concentrates on three topics: MOST RF Circuits; Bandpass Delta-Sigma Converters; Translinear Circuits. The book comprises six papers on each topic written by internationally recognised experts. These papers are tutorial in nature and together make a substantial contribution to improving the design of analog circuits. The book is divided into three parts: Part I, MOST RF Circuits, demonstrates the viability of using CMOS for high-frequency communication applications. This renaissance in radio-frequency design is largely driven by the explosion of interest in telecommunications and several of the papers are specifically targeted to wireless communication applications. Part II, Bandpass Delta-Sigma Converters, describes the latest developments in analog-to-digital and digital-to-analog converters. These converters find applications in telecommunications, hearing aids and audio systems, particularly when they consume low-power and have high performance. This part concludes by looking at the CAD tools required for the design of such converters. Part III, Translinear Circuits, have become important devices in building analog linear functions with variable parameters. This part of the book presents the latest research and techniques for designing Translinear Circuits using both bipolar and CMOS technologies. Analog Circuit Design is an essential reference source for analog design engineers and researchers wishing to keep abreast with the latest developments in the field. The tutorial nature of the contributions also makes it suitable for use in an advanced course.

Improving the performance of the power amplifier is the most pressing problem facing designers of modern radio-frequency (RF) transceivers. Linearity and power efficiency of the transmit path are of utmost importance, and the power amplifier has proven to be the bottleneck for both. High linearity enables transmission at the highest data rates for a given channel bandwidth, and power efficiency prolongs battery lifetime in portable units and reduces heat dissipation in high-power transmitters. Cartesian feedback is a power amplifier linearization technique that acts to soften the tradeoff between power efficiency and linearity in power amplifiers. Despite its compelling, fundamental advantages, the technique has not enjoyed widespread acceptance because of certain implementation difficulties.
Feedback Linearization of RF Power Amplifiers introduces new techniques for overcoming the challenges faced by the designer of a Cartesian feedback system. The theory of the new techniques are described and analyzed in detail. The book culminates with the results of the first known fully integrated Cartesian feedback power amplifier system, whose design was enabled by the techniques described.
Feedback Linearization of RF Power Amplifiers is a valuable reference work for engineers in the telecommunications industry, industry researchers, academic researchers.

This work is aimed at practitioners wishing to gain a broader systems-based perspective of phase-locked loops; and is also suitable as a graduate text for engineering students. It provides detailed coverage of digital sampling effects in modern phase-locked frequency synthesizers from a systems perspective, and discusses all aspects of phase noise, its mathematical modelling and its impact upon different digital communication systems. Sections on building blocks for frequency synthesis using phase-locked loops, frequency synthesis using sampled-data control systems, and MASCET, are included.

Abstraction Refinement for Large Scale Model Checking summarizes recent research on abstraction techniques for model checking large digital system. Considering both the size of today's digital systems and the capacity of state-of-the-art verification algorithms, abstraction is the only viable solution for the successful application of model checking techniques to industrial-scale designs. This book describes recent research developments in automatic abstraction refinement techniques. The suite of algorithms presented in this book has demonstrated significant improvement over prior art; some of them have already been adopted by the EDA companies in their commercial/in-house verification tools.

Silicon-On-Insulator (SOI) CMOS technology has been regarded as another major technology for VLSI in addition to bulk CMOS technology. Owing to the buried oxide structure, SOI technology offers superior CMOS devices with higher speed, high density, and reduced second order effects for deep-submicron low-voltage, low-power VLSI circuits applications. In addition to VLSI applications, and because of its outstanding properties, SOI technology has been used to realize communication circuits, microwave devices, BICMOS devices, and even fiber optics applications. CMOS VLSI Engineering: Silicon-On-Insulator addresses three key factors in engineering SOI CMOS VLSI - processing technology, device modelling, and circuit designs are all covered with their mutual interactions. Starting from the SOI CMOS processing technology and the SOI CMOS digital and analog circuits, behaviors of the SOI CMOS devices are presented, followed by a CAD program, ST-SPICE, which incorporates models for deep-submicron fully-depleted mesa-isolated SOI CMOS devices and special purpose SOI devices including polysilicon TFTs. CMOS VLSI Engineering: Silicon-On-Insulator is written for undergraduate senior students and first-year graduate students interested in CMOS VLSI. It will also be suitable for electrical engineering professionals interested in microelectronics.

This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design.

Reviewing the various IC packaging, assembly, and interconnection technologies, this professional reference provides an overview of the materials and the processes, as well as the trends and available options that encompass electronic manufacturing. It covers both the technical issues and touches on some of the reliability concerns with the various technologies applicable to packaging and assembly of the IC. The book discusses the various packaging approaches, assembly options, and essential manufacturing technologies, among other relevant topics.

A major advantage of a direct digital synthesizer is that its output frequency, phase and amplitude can be precisely and rapidly manipulated under digital processor control. This book was written to find possible applications for radio communication systems.

Today's booming expanse of personal wireless radio communications is a rich source of new challenges for the designer of the underlying enabling te- nologies. Personal communication networks are designed from a fundam- tally different perspective than broadcast service networks, such as radio and television. While the focus of the latter is on reliability and user comfort, the emphasis of personal communication devices is on throughput and mobility. However, because the wireless channel is a shared transmission medium with only very limited resources, a trade-off has to be made between mobility and the number of simultaneous users in a con?ned geographical area. Accord- 1 ing to Shannon's theorem on channel capacity, the overall data throughput of a communication channel bene?ts from either a linear increase of the tra- mission bandwidth, or an (equivalent) exponential increase in signal quality. Consequently, it is more bene?cial to think in terms of channel bandwidth than it is to pursue a high transmission power. All the above elements are embodied in the concept of spatial ef?ciency. By describing the throughput of a system 2 in terms of bits/s/Hz/m , spatial ef?ciency takes into account that the use of a low transmission power reduces the operational range of a radio transmission, and as such enables a higher reuse rate of the same frequency spectrum.

Static and Dynamic Performance Limitations for High Speed D/A Converters discusses the design and implementation of high speed current-steering CMOS digital-to-analog converters.
Starting from the definition of the basic specifications for a D/A converter, the elements determining the static and dynamic performance are identified. Different guidelines based on scientific derivations are suggested to optimize this performance. Furthermore, a new closed formula has been derived to account for the influence of the transistor mismatch on the achievable resolution of the current-steering D/A converter. To allow a thorough understanding of the dynamic behavior, a new factor has been introduced. Moreover, the frequency dependency of the output impedance introduces harmonic distortion components which can limit the maximum attainable spurious free dynamic range. Finally, the last part of the book gives an overview on different existing transistor mismatch models and the link with the static performance of the D/A converter.

This book is about large-scale electronic circuits design driven by nanotechnology, where nanotechnology is broadly defined as building circuits using nanoscale devices that are either implemented with nanomaterials (e.g., nanotubes or nanowires) or following an unconventional method (e.g., FinFET or III/V compound-based devices). These nanoscale devices have significant potential to revolutionize the fabrication and integration of electronic systems and scale beyond the perceived scaling limitations of traditional CMOS. While innovations in nanotechnology originate at the individual device level, realizing the true impact of electronic systems demands that these device-level capabilities be translated into system-level benefits. This is the first book to focus on nanoscale circuits and their design issues, bridging the existing gap between nanodevice research and nanosystem design.

The VHSIC Hardware Description Language (VHDL) provides a standard machine processable notation for describing hardware. VHDL is the result of a collaborative effort between IBM, Intermetrics, and Texas Instruments; sponsored by the Very High Speed Integrated Cir cuits (VHSIC) program office of the Department of Defense, beginning in 1981. Today it is an IEEE standard (1076-1987), and several simulators and other automated support tools for it are available commercially. By providing a standard notation for describing hardware, especially in the early stages of the hardware design process, VHDL is expected to reduce both the time lag and the cost involved in building new systems and upgrading existing ones. VHDL is the result of an evolutionary approach to language devel opment starting with high level hardware description languages existing in 1981. It has a decidedly programming language flavor, resulting both from the orientation of hardware languages of that time, and from a ma jor requirement that VHDL use Ada constructs wherever appropriate. During the 1980's there has been an increasing current of research into high level specification languages for systems, particularly in the software area, and new methods of utilizing specifications in systems de velopment. This activity is worldwide and includes, for example, object oriented design, various rigorous development methods, mathematical verification, and synthesis from high level specifications. VAL (VHDL Annotation Language) is a simple further step in the evolution of hardware description languages in the direction of applying new methods that have developed since VHDL was designed."

Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested.
1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.

2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash.

3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.

Semiconductor power electronics plays a dominant role due its increased efficiency and high reliability in various domains including the medium and high electrical drives, automotive and aircraft applications, electrical power conversion, etc. Power/HVMOS Devices Compact Modeling will cover very extensive range of topics related to the development and characterization power/high voltage (HV) semiconductor technologies as well as modeling and simulations of the power/HV devices and smart power integrated circuits (ICs). Emphasis is placed on the practical applications of the advanced semiconductor technologies and the device level compact/spice modeling. This book is intended to provide reference information by selected, leading authorities in their domain of expertise. They are representing both academia and industry. All of them have been chosen because of their intimate knowledge of their subjects as well as their ability to present them in an easily understandable manner.

Addressing the rising security issues during the design stages of cyber-physical systems, this book develops a systematic approach to address security at early design stages together with all other design constraints. Cyber-attacks become more threatening as systems are becoming more connected with the surrounding environment, infrastructures, and other systems. Security mechanisms can be designed to protect against attacks and meet security requirements, but there are many challenges of applying security mechanisms to cyber-physical systems including open environments, limited resources, strict timing requirements, and large number of devices. Designed for researchers and professionals, this book is valuable for individuals working in network systems, security mechanisms, and system design. It is also suitable for advanced-level students of computer science.

Analog and mixed signal integrated systems of today and tomorrow will be very complex, as they meet the challenge and increased demand for higher levels of integration in a System on Chip (SoC). Current and future trends call for pushing system integration to the highest levels in order to achieve low cost and low power for large volume products in the consumer and telecom markets, such as feature-rich handheld battery-operated devices. In todaya (TM)s analog design environment, a fully integrated CMOS SoC design may require several silicon spins before it meets all product specifications and often with relatively low yields. This results in significant increase in development cost, especially that mask set costs increase exponentially as feature size scales down.

This book is devoted to the subject of adaptive techniques for smart analog and mixed signal design whereby fully functional first-pass silicon is achievable. To our knowledge, this is the first book devoted to this subject. The techniques described should lead to quantum improvement in design productivity of complex analog and mixed signal systems while significantly cutting the spiraling costs of product development in emerging nanometer technologies. The underlying principles and design techniques presented are generic and would certainly apply to CMOS analog and mixed signal platforms in high volume, low-cost wireless, wire line, and consumer electronic SoC or chip set solutions.

Adaptive Techniques for Mixed Signal Sytem on Chip discusses the concept of adaptation in the context of analog and mixed signal design along with different adaptive architectures used to control any system parameter. The first part ofthe book gives an overview of the different elements that are normally used in adaptive designs including tunable elements as well as voltage, current, and time references with an emphasis on the circuit design of specific blocks such as voltage-controlled transconductors, offset comparators, and a novel technique for accurate implementation of on chip resistors. While the first part of the book addresses adaptive techniques at the circuit and block levels, the second part discusses adaptive equalization architectures employed to minimize the impact of ISI (Intersymbol Interference) on the quality of received data in high-speed wire line transceivers. It presents the implementation of a 125Mbps transceiver operating over a variable length of Category 5 (CAT-5) Ethernet cable as an example of adaptive equalizers.

The automation of layout synthesis design under stringent timing specifications is essential for state-of-the-art VLSI circuits and systems design. Especially, the timing-driven layout synthesis with optimal placement and routing of transistors with proper sizing is most critical in view of the chip area, interconnection parasitics, circuit delay and power dissipation. This book presents a systematic and unified view of the layout synthesis problem with a strong focus on CMOS technology. The criticality of RC parasitics in the interconnects and the optimal sizing of both p-channel and n-channel translators are illustrated for motivation. Following the motivation, the problems of modeling circuit delays and translator sizing are formulated and solved with mathematical rigor. Various delay models for CMOS circuits are discussed to account for realistic interconnection parasitics, the effect of transistor sizes, and also the input slew rates. Also many of the efficient transistor sizing algorithms are critically reviewed and the most recent transistor sizing algorithm based on convex programming techniques is introduced. For design automation of the rigorous CMOS layout synthesis, an integrated system that employs a suite of functional modules is introduced for step-by-step illustration of the design optimization process that produces highly compact CMOS layouts that meet user-specified timing and logical netlist requirements. Through most rigorous discussion of the essential design automation process steps and important models and algorithms this book presents a unified systems approach that can be practiced for high-performance CMOS VLSI designs. This book serves as an excellentreference, and can be used as text in advanced courses covering VLSI design, especially for design automation of physical design.

Sigma Delta converters are a very popular choice for the A/D converter in multi-standard, mobile and cellular receivers. Key A/D converter specifications are high dynamic range, robustness, scalability, low-power and low EMI. "Robust Sigma Delta Converters "presents a requirement derivation of a Sigma Delta modulator applied in a receiver for cellular and connectivity, and shows trade-offs between RF and ADC. The book proposes to categorize these requirements in 5 quality indicators which can be used to qualify a system, namely accuracy, robustness, flexibility, efficiency and emission. In the book these quality indicators are used to categorize Sigma Delta converter theory. A few highlights on each of these quality indicators are; Quality indicators: provide a means to quantify system quality.Accuracy: introduction of new Sigma Delta Modulator architectures.Robustness: a significant extension on clock jitter theory based on phase and error amplitude error models. Extension of the theory describing aliasing in Sigma Delta converters for different types of DACs in the feedback loop. Flexibility: introduction of a Sigma Delta converter bandwidth scaling theory leading to very flexible Sigma Delta converters. Efficiency: introduction of new Figure-of-Merits which better reflect performance-power trade-offs. Emission: analysis of Sigma Delta modulators on emission is not part of the book

The quality indicators also reveal that, to exploit nowadays advanced IC technologies, things should be done as much as possible digital up to a limit where system optimization allows reducing system margins. At the end of the book Sigma Delta converter implementations are shown which are digitized on application-, architecture-, circuit- and layout-level.

"Robust Sigma Delta Converters "is written under the assumption that the reader has some background in receivers and in A/D conversion.

CMOS Current Amplifiers presents design strategies for high performance current amplifiers based on CMOS technology. After an introduction to various architectures of operational amplifiers, the operating principles of the current amplifier are outlined. This book provides the reader with simple and compact design equations for use in a pencil and paper design and the following simulation step. Chapter 1 introduces the general aspects of current amplifiers. After a preliminary classification of operational amplifiers, ideal blocks and models are discussed for different architectures and a first high-level comparison is made between traditional amplifiers and current amplifiers. Analysis and examples of basic circuits, as well as signal processing applications involving current amplifiers, are also given. Non-idealities and second- order effects causing limitations in performance are then discussed and evaluated. Chapter 2 focuses on low-drive current amplifiers. Several design examples for current conveyors and class A current amplifiers are discussed in detail and design equations are presented for the main performance parameters, which allows a good trade-off between requirements. High-performance solutions for high bandwidth and low voltage capability are also considered, and, finally, current comparators with progressively enhanced performance are reported and analyzed critically. Chapter 3 deals with current amplifiers for off-chip loads. Several class AB current-mode output stages are discussed and design strategies which improve performance are presented. A detailed analysis of non-ideal effect is carried out with particular emphasis on linearity. Design examples are given and circuit arrangements for further developments are included. CMOS Current Amplifiers serves as an excellent reference for researchers and professionals of analog IC design, and may also be used as an advanced text on current amplifiers.

This book describes the structured design and optimization of efficient, energy processing integrated circuits. The approach is multidisciplinary, covering the monolithic integration of IC design techniques, power electronics and control theory. In particular, this book enables readers to conceive, synthesize, design and implement integrated circuits with high-density high-efficiency on-chip switching power regulators. Topics covered encompass the structured design of the on-chip power supply, efficiency optimization, IC-compatible power inductors and capacitors, power MOSFET switches and efficient switch drivers in standard CMOS technologies.

This book describes a circuit architecture for converting real analog signals into a digital format, suitable for digital signal processors. This architecture, referred to as multi-stage noise-shaping (MASH) Continuous-Time Sigma-Delta Modulators (CT- M), has the potential to provide better digital data quality and achieve better data rate conversion with lower power consumption. The authors not only cover MASH continuous-time sigma delta modulator fundamentals, but also provide a literature review that will allow students, professors, and professionals to catch up on the latest developments in related technology.

This leading-edge circuit design resource offers the knowledge needed to quickly pinpoint transmission problems that can compromise circuit design. Discusses both design and debug issues at gigabit per second data rates.

In the last two decades semiconductor device simulation has become a research area, which thrives on a cooperation of physicists, electrical engineers and mathe maticians. In this book the static semiconductor device problem is presented and analysed from an applied mathematician's point of view. I shall derive the device equations - as obtained for the first time by Van Roosbroeck in 1950 - from physical principles, present a mathematical analysis, discuss their numerical solu tion by discretisation techniques and report on selected device simulation runs. To me personally the most fascinating aspect of mathematical device analysis is that an interplay of abstract mathematics, perturbation theory, numerical analysis and device physics is prompting the design and development of new technology. I very much hope to convey to the reader the importance of applied mathematics for technological progress. Each chapter of this book is designed to be as selfcontained as possible, however, the mathematical analysis of the device problem requires tools which cannot be presented completely here. Those readers who are not interested in the mathemati cal methodology and rigor can extract the desired information by simply ignoring details and proofs of theorems. Also, at the beginning of each chapter I refer to textbooks which introduce the interested reader to the required mathematical concepts."