The tremendous growth in wireless and mobile communications has placed stringent requirements on channel spacing and, by implication, on the phase noise of oscillators. Compounding the challenge has been a recent drive toward implementations of transceivers in CMOS, whose inferior l/f noise performance has usually been thought to disqualify it from use in all but the lowest-performance oscillators. Low noise oscillators are also highly desired in the digital world. The continued drive toward higher clock frequencies translates into a demand for ever-decreasing jitter. There is a need for a deep understanding of the fundamental mechanisms governing the process by which device, substrate, and supply noise turn into jitter and phase noise. Existing models generally offer only qualitative insights, however, and it has not always been clear why they are not quantitatively correct. The Design of Low Noise Oscillators offers a new time-variant phase noise model. By discarding the implicit assumption of time- invariance underlying many other approaches, this model is capable of making quantitative predictions of the phase noise and jitter of different types of oscillators. It is able to attribute a definite amount of phase noise to every noise source in the circuit. Because of its time-variant nature, the model also takes into account the effect of cyclostationary noise sources in a natural way. It details the precise mechanism by which low frequency noise, such as l/f noise, upconverts into close-in phase noise. An important new understanding is that rise and fall time symmetry controls such upconversion. More important, it suggests practical methods for suppressing this upconversion, so thatgood oscillators can be built in technologies with notoriously poor l/f noise performance (such as CMOS or GaAs MESFET). The Design of Low Noise Oscillators will be of interest to both analog and digital circuit as well as RF circuit designers.

This work presents an introduction, by leading experts in the field, to optical designs for handling the efficient routing of photonic information. This book fully explains electrical versus optical issues, the promise and diversity of optical interconnection, and the advantages, costs and tradeoffs. The reproducability, manufacturability, testability, and reliability are discussed at length for each design approach given. The text rigorously examines the real optical interconnection issues.

This book illustrates a variety of circuit designs on plastic foils and provides all the information needed to undertake successful designs in large-area electronics. The authors demonstrate architectural, circuit, layout, and device solutions and explain the reasons and the creative process behind each. Readers will learn how to keep under control large-area technologies and achieve robust, reliable circuit designs that can face the challenges imposed by low-cost low-temperature high-throughput manufacturing.

Automatic Modulation Classification (AMC) has been a key technology in many military, security, and civilian telecommunication applications for decades. In military and security applications, modulation often serves as another level of encryption; in modern civilian applications, multiple modulation types can be employed by a signal transmitter to control the data rate and link reliability. This book offers comprehensive documentation of AMC models, algorithms and implementations for successful modulation recognition. It provides an invaluable theoretical and numerical comparison of AMC algorithms, as well as guidance on state-of-the-art classification designs with specific military and civilian applications in mind. Key Features: * Provides an important collection of AMC algorithms in five major categories, from likelihood-based classifiers and distribution-test-based classifiers to feature-based classifiers, machine learning assisted classifiers and blind modulation classifiers * Lists detailed implementation for each algorithm based on a unified theoretical background and a comprehensive theoretical and numerical performance comparison * Gives clear guidance for the design of specific automatic modulation classifiers for different practical applications in both civilian and military communication systems * Includes a MATLAB toolbox on a companion website offering the implementation of a selection of methods discussed in the book

This book presents innovative solutions in the design of precision instrumentation amplifier and read-out ICs, which can be used to boost millivolt-level signals transmitted by modern sensors, to levels compatible with the input ranges of typical Analog-to-Digital Converters (ADCs). The discussion includes the theory, design and realization of interface electronics for bridge transducers and thermocouples. It describes the use of power efficient techniques to mitigate low frequency errors, resulting in interface electronics with high accuracy, low noise and low drift. Since this book is mainly about techniques for eliminating low frequency errors, it describes the nature of these errors and the associated dynamic offset cancellation techniques used to mitigate them."

This practical guide and introduction to the design of key RF building blocks used in high data rate transmitters emphasizes CMOS circuit techniques applicable to oscillators and upconvertors. The book is written in an easily accessible manner, without losing detail on the technical side.

The rapidly growing photovoltaic industry is expanding the need for education and training worldwide, particularly at the system level. Modelling Photovoltaic Systems using PSpice provides expert help in understanding photovoltaic systems engineering and system design. Working with PSpice, the most popular standard for analogue and mixed signal simulation, the book allows detailed and quantitative analysis of design concepts, criteria and results.

Featuring:

• Both topological and behavioural models for the key components helping short- and long-term simulation.

• A model to compute the Loss of Load probability, considering year long daily radiation data.

• Sizing procedures for stand-alone and grid connected systems, based on energy balance and long-term simulations.

• Models for PV generators, batteries, converters and inverters.

• Coverage of numerous topics related to small PV systems, such as artificial light response, random irradiance and illuminance conditions

• A comprehensive range of solved examples

Fine pitch high lead count integrated circuit packages represent a dramatic change from the conventional methods of assembling electronic components to a printed interconnect circuit board. To some, these FPTpackages appear to bean extension of the assembly technology called surface mount or SMT. Many of us who have spent a significant amount of time developing the process and design techniques for these fine pitchpackages haveconcluded that these techniquesgobeyondthose commonly useed for SMT. In 1987 the presentauthor, convincedofthe uniqueness ofthe assembly and design demands ofthese packages, chaired ajoint committee where the members agreed to use fine pitch technology (FPT) as the defining term for these demands. The committee was unique in several ways, one being that it was the first time three U. S. standards organizations, the IPC (Lincolnwood, IL), theEIA(Washington, D. C. ), and theASTM (Philadelphia), cametogether tocreate standards before a technology was in high demand. The term fine pitch technology and its acronym FPT have since become widely accepted in the electronics industry. The knowledge of the terms and demands of FPT currently exceed the usage of FPT packaged components, but this is changing rapidly because of the size, performance, and cost savings of FPT. I have resisted several past invitations to write other technical texts. However, I feel there are important advantages and significant difficulties to be encountered with FP

Despite the fact that in the digital domain, designers can take full benefits of IPs and design automation tools to synthesize and design very complex systems, the analog designers' task is still considered as a 'handcraft', cumbersome and very time consuming process. Thus, tremendous efforts are being deployed to develop new design methodologies in the analog/RF and mixed-signal domains. This book collects 16 state-of-the-art contributions devoted to the topic of systematic design of analog, RF and mixed signal circuits. Divided in the two parts Methodologies and Techniques recent theories, synthesis techniques and design methodologies, as well as new sizing approaches in the field of robust analog and mixed signal design automation are presented for researchers and R/D engineers.

"A results-oriented book. Quality line drawings, lucid photography, and informative graphs are used generously... The theoretical rigor of each chapter amply supports the real-world design examples that follow." -- Sensors Magazine

"One of the few sources to offer such comprehensive coverage." -- IEEE Electrical Insulation

Systematic Design of Sigma-Delta Analog-to-Digital Converters describes the issues related to the sigma-delta analog-to-digital converters (ADCs) design in a systematic manner: from the top level of abstraction represented by the filters defining signal and noise transfer functions (STF, NTF), passing through the architecture level where topology-related performance is calculated and simulated, and finally down to parameters of circuit elements like resistors, capacitors, and amplifier transconductances used in individual integrators. The systematic approach allows the evaluation of different loop filters (order, aggressiveness, discrete-time or continuous-time implementation) with quantizers varying in resolution. Topologies explored range from simple single loops to multiple cascaded loops with complex structures including more feedbacks and feedforwards. For differential circuits, with switched-capacitor integrators for discrete-time (DT) loop filters and active-RC for continuous-time (CT) ones, the passive integrator components are calculated and the power consumption is estimated, based on top-level requirements like harmonic distortion and noise budget.
This unified, systematic approach to choosing the best sigma-delta ADC implementation for a given design target yields an interesting solution for a high-resolution, broadband (DSL-like) ADC operated at low oversampling ratio, which is detailed down to transistor-level schematics.
The target audience of Systematic Design of Sigma-Delta Analog-to-Digital Converters are engineers designing sigma-delta ADCs and/or switched-capacitor and continuous-time filters, both beginners and experienced. It is also intended forstudents/academics involved in sigma-delta and analog CAD research.

The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solutions follows a similar approach. This is an area of processor design that is still in its early stages of exploration and that holds the promise of accomplishing the ultimate goal of achieving complete correctness guarantees for microprocessor-based computation. The authors conclude the book with a look towards the future of late-stage verification and its growing role in the processor life-cycle.

CMOS Memory Circuits is a systematic and comprehensive reference work designed to aid in the understanding of CMOS memory circuits, architectures, and design techniques. CMOS technology is the dominant fabrication method and almost the exclusive choice for semiconductor memory designers. Both the quantity and the variety of complementary-metal-oxide-semiconductor (CMOS) memories are staggering. CMOS memories are traded as mass-products worldwide and are diversified to satisfy nearly all practical requirements in operational speed, power, size, and environmental tolerance. Without the outstanding speed, power, and packing density characteristics of CMOS memories, neither personal computing, nor space exploration, nor superior defense systems, nor many other feats of human ingenuity could be accomplished. Electronic systems need continuous improvements in speed performance, power consumption, packing density, size, weight, and costs. These needs continue to spur the rapid advancement of CMOS memory processing and circuit technologies. CMOS Memory Circuits is essential for those who intend to (1) understand, (2) apply, (3) design and (4) develop CMOS memories.

With the development of Very-Deep Sub-Micron technologies, process variability is becoming increasingly important and is a very important issue in the design of complex circuits. Process variability is the statistical variation of process parameters, meaning that these parameters do not have always the same value, but become a random variable, with a given mean value and standard deviation. This effect can lead to several issues in digital circuit design.

The logical consequence of this parameter variation is that circuit characteristics, as delay and power, also become random variables. Because of the delay variability, not all circuits will now have the same performance, but some will be faster and some slower. However, the slowest circuits may be so slow that they will not be appropriate for sale. On the other hand, the fastest circuits that could be sold for a higher price can be very leaky, and also not very appropriate for sale. A main consequence of power variability is that the power consumption of some circuits will be different than expected, reducing reliability, average life expectancy and warranty of products. Sometimes the circuits will not work at all, due to reasons associated with process variations. At the end, these effects result in lower yield and lower profitability.

To understand these effects, it is necessary to study the consequences of variability in several aspects of circuit design, like logic gates, storage elements, clock distribution, and any other that can be affected by process variations. The main focus of this book will be storage elements.

Enables the reader to test an analog circuit that is implemented either in bipolar or MOS technology.

Examines the testing and fault diagnosis of analog and analog part of mixed signal circuits.

Covers the testing and fault diagnosis of both bipolar and Metal Oxide Semiconductor (MOS) circuits and introduces .

Also contains problems that can be used as quiz or homework.

This comprehensive and insightful book discusses ESD protection circuit design problems from an IC designer's perspective. On-Chip ESD Protection for Integrated Circuits: An IC Design Perspective provides both fundamental and advanced materials needed by a circuit designer for designing ESD protection circuits, including:

• Testing models and standards adopted by U.S. Department of Defense, EIA/JEDEC, ESD Association, Automotive Electronics Council, International Electrotechnical Commission, etc.
• ESD failure analysis, protection devices, and protection of sub-circuits
• Whole-chip ESD protection and ESD-to-circuit interactions
• Advanced low-parasitic compact ESD protection structures for RF and mixed-signal IC's
• Mixed-mode ESD simulation-design methodologies for design prediction ESD-to-circuit interactions, and more!

The interest for :I:~ modulation-based NO converters has significantly increased in the last years. The reason for that is twofold. On the one hand, unlike other converters that need accurate building blocks to obtain high res olution, :I:~ converters show low sensitivity to the imperfections of their building blocks. This is achieved through extensive use of digital signal pro cessing - a desirable feature regarding the implementation of NO interfaces in mainstream CMOS technologies which are better suited for implementing fast, dense, digital circuits than accurate analog circuits. On the other hand, the number of applications with industrial interest has also grown. In fact, starting from the earliest in the audio band, today we can find :I:~ converters in a large variety of NO interfaces, ranging from instrumentation to commu nications. These advances have been supported by a number of research works that have lead to a considerably large amount of published papers and books cov ering different sub-topics: from purely theoretical aspects to architecture and circuit optimization. However, so much material is often difficultly digested by those unexperienced designers who have been committed to developing a :I:~ converter, mainly because there is a lack of methodology. In our view, a clear methodology is necessary in :I:~ modulator design because all related tasks are rather hard.

Although exploratory and developmental activity in electron beam testing (EBT) 25 years, it was not had already been in existence in research laboratories for over until the beginning of the 1980s that it was taken up seriously as a technique for integrated circuit (IC) testing. While ICs were being fabricated on design rules of several microns, the mechanical ne edle probe served quite adequately for internal chip probing. This scenario changed with growing device complexity and shrinking geometries, prompting IC manufacturers to take note ofthis new testing technology. It required several more years and considerable investment by electron beam tester manufacturers, however, to co me up with user-friendly automated systems that were acceptable to IC test engineers. These intervening years witnessed intense activity in the development of instrumentation, testing techniques, and system automation, as evidenced by the proliferation of technical papers presented at conferences. With the shift of interest toward applications, the technology may now be considered as having come of age.

From the reviews: ..". this is a well produced book, written in a easy to read style, and will also be a very useful primer for someone starting out the field ...], and a useful source of reference for experienced users ..." Microelectronics Journal

Modeling of Induction Motors with One and Two Degrees of Mechanical Freedom will be of interest to electrical engineering academics and graduate students as well as electric machine designers and engineers involved in control, mechatronics, and automation.
This book presents the mathematical model of induction motors with two degrees of mechanical freedom (IM-2DMF), formed in the electromagnetic field as well as in circuit theory, which allows analyzing the performance of these three groups of motors taking into account edge effects, winding and current asymmetry. The model derived is based on the concept of magnetic field wave moving in the air-gap with a helical motion. In general, the rotor moves helically too with the rotary-linear slip. The electromagnetic field as well as motor performance of the particular motors is analyzed.
The mathematical model of IM-2DMF is more general to the model of induction motors with one degree of mechanical freedom, i.e. rotary and linear motors. Examples of modeling two types of rotary disc motors and flat linear motor with twisted primary part are presented with inclusion of finite stator and rotor length and width effects. The simulation results are backed by the measurements carried out on the laboratory models, which were tested on the unique measurement stand.
By presenting the theory of a group of induction motors with two degrees of mechanical freedom and giving a basis for designing of these type of motors, as well as to give the tool for analysis of their performance, Modeling of Induction Motors with One and Two Degrees of Mechanical Freedom is a must-have book for electrical engineering graduate students and electric machine designers and engineers.

This book discusses various aspects, challenges, and solutions for developing systems-of-systems for situation awareness, using applications in the domain of maritime safety and security. Topics include advanced, multi-objective visualization methods for situation awareness, stochastic outlier selection, rule-based anomaly detection, an ontology-based event model for semantic reasoning, new methods for semi-automatic generation of adapters bridging communication gaps, security policies for systems-of-systems, trust assessment, and methods to deal with the dynamics of systems-of-systems in run-time monitoring, testing, and diagnosis. Architectural considerations for designing information-centric systems-of-systems such as situation awareness systems, and an integrated demonstrator implementing many of the investigated aspects, complete the book.

High-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters as follows. Chapter 1 provides an overview to the design of clock networks. Chapter 2 specifies the timing requirements in digital design. Chapter 3 shows the circuits of sequential elements including latches and flip-flops. Chapter 4 describes the domino circuits, which need special clock signals. Chapter 5 discusses the phase-locked loop (PLL) and delay-locked loop (DLL), which provide the clock generation and de-skewing for the on-chip clock distribution. Chapter 6 summarizes the clock distribution techniques published in the state-of-the-art microprocessor chips. Chapter 7 describes the CAD flow on the clock network simulation. Chapter 8 gives the research work on low-voltage swing clock distribution. Chapter 9 explores the possibility of placing the global clock tree on the package layers. Chapter 10 shows the algorithms of balanced clock routing and wire sizing for the skew minimization. Chapter 11 shows a commercial CAD tool that deals with clock tree synthesis in the ASIC design flow. The glossary is attached at the end of this book. The clock network design is still a challenging task in most high-speed VLSI chips, since the clock frequency and power consumption requirements are increasingly difficult to meet for multiple clock networks on the chip. Many research works and industry examples will be shown in this area to continually improve the clock distribution networks for future high-performance chips.

Low-Voltage CMOS Log Companding Analog Design presents in detail state-of-the-art analog circuit techniques for the very low-voltage and low-power design of systems-on-chip in CMOS technologies. The proposed strategy is mainly based on two bases: the Instantaneous Log Companding Theory, and the MOSFET operating in the subthreshold region. The former allows inner compression of the voltage dynamic-range for very low-voltage operation, while the latter is compatible with CMOS technologies and suitable for low-power circuits. The required background on the specific modeling of the MOS transistor for Companding is supplied at the beginning. Following this general approach, a complete set of CMOS basic building blocks is proposed and analyzed for a wide variety of analog signal processing. In particular, the covered areas include: amplification and AGC, arbitrary filtering, PTAT generation, and pulse duration modulation (PDM). For each topic, several case studies are considered to illustrate the design methodology. Also, integrated examples in 1.2um and 0.35um CMOS technologies are reported to verify the good agreement between design equations and experimental data. The resulting analog circuit topologies exhibit very low-voltage (i.e. 1V) and low-power (few tenths of uA) capabilities. Apart from these specific design examples, a real industrial application in the field of hearing aids is also presented as the main demonstrator of all the proposed basic building blocks. This system-on-chip exhibits true 1V operation, high flexibility through digital programmability and very low-power consumption (about 300uA including the Class-D amplifier). As a result, the reported ASIC can meet the specifications of a complete family of common hearing aid models. In conclusion, this book is addressed to both industry ASIC designers who can apply its contents to the synthesis of very low-power systems-on-chip in standard CMOS technologies, as well as to the teachers of modern circuit design in electronic engineering.

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.