This volume addresses the low-power low-voltage Sigma-Delta ADC design in nanometer CMOS technologies at both the circuit-level and the system level. The low-power low-voltage Sigma-Delta modulator design at the circuit level is introduced. A design example is presented in this book. This design is the first published Sigma-Delta design in a 90-nm CMOS technology and reaches a very high figure-of-merit. At the system level, a novel systematic study on the full feedforward Sigma-Delta topology is presented in this book. As a design example, a fourth-order single-loop full feedforward Sigma-Delta modulator design in a 130-nm pure digital CMOS technology is presented. This design is the first design using the full feedforward Sigma-Delta topology and reaches the highest conversion speed among all the 1-V Sigma-Delta modulators to date.

This book describes an ECG processing architecture that guides biomedical SoC developers, from theory to implementation and testing. The authors provide complete coverage of the digital circuit implementation of an ultra-low power biomedical SoC, comprised of a detailed description of an ECG processor implemented and fabricated on chip. Coverage also includes the challenges and tradeoffs of designing ECG processors. Describes digital circuit architecture for implementing ECG processing algorithms on chip; Includes coverage of signal processing techniques for ECG processing; Features ultra-low power circuit design techniques; Enables design of ECG processing architectures and their respective on-chip implementation.

This "current-amplifier cookbook" contains an extensive review of different current amplifier topologies realisable with modern CMOS integration technologies. The book derives the seldom-discussed issue of high-frequency distortion performance for all reviewed amplifier topologies, using as simple and intuitive mathematical methods as possible.

This book provides readers with a state-of-the-art description of techniques to be used for ultra-low-power (ULP) and ultra-low-cost (ULC), short-range wireless receivers. Readers will learn what is required to deploy these receivers in short-range wireless sensor networks, which are proliferating widely to serve the internet of things (IoT) for "smart cities." The authors address key challenges involved with the technology and the typical tradeoffs between ULP and ULC. Three design examples with advanced circuit techniques are described in order to address these trade-offs, which special focus on cost minimization. These three techniques enable respectively, cascading of radio frequency (RF) and baseband (BB) circuits under an ultra-low-voltage (ULV) supply, cascading of RF and BB circuits in current domain for current reuse and a novel function-reuse receiver architecture, suitable for ULV and multi-band ULP applications such as the sub-GHz ZigBee.

The time has come for high-level synthesis. When research into synthesizing hardware from abstract, program-like de scriptions started in the early 1970' s, there was no automated path from the register transfer design produced by high-level synthesis to a complete hardware imple mentation. As a result, it was very difficult to measure the effectiveness of high level synthesis methods; it was also hard to justify to users the need to automate architecture design when low-level design had to be completed manually. Today's more mature CAD techniques help close the gap between an automat ically synthesized design and a manufacturable design. Market pressures encour age designers to make use of any and all automated tools. Layout synthesis, logic synthesis, and specialized datapath generators make it feasible to quickly imple ment a register-transfer design in silicon, leaving designers more time to consider architectural improvements. As IC design becomes more automated, customers are increasing their demands; today's leading edge designers using logic synthesis systems are training themselves to be tomorrow's consumers of high-level synthe sis systems. The need for very fast turnaround, a competitive fabrication market WhlCh makes small-quantity ASIC manufacturing possible, and the ever growing co: n plexity of the systems being designed, all make higher-level design automaton inevitable."

This book addresses the need for models and techniques to predict stability boundaries, given trends toward miniaturization of switching power supplies in battery-operated portable devices, which lead to the exhibition of fast-scale chaotic instabilities. The authors describe a method to predict stability boundaries from a design-oriented perspective, which captures the effect of the different parameters of the system upon the particular boundary. Unlike previous methods involving complex analysis based on the discrete-time mathematical model, the method introduced here allows for prediction of the overall stability boundaries within the complete design space and is based upon a simple design-oriented index."

This book is the first in aseries on novellow power design architectures, methods and design practices. It results from of a large European project started in 1997, whose goal is to promote the further development and the faster and wider industrial use of advanced design methods for reducing the power consumption of electronic systems. Low power design became crucial with the wide spread of portable information and cornrnunication terminals, where a small battery has to last for a long period. High performance electronics, in addition, suffers from a permanent increase of the dissipated power per square millimetre of silicon, due to the increasing eIock-rates, which causes cooling and reliability problems or otherwise limits the performance. The European Union's Information Technologies Programme 'Esprit' did there fore launch a 'Pilot action for Low Power Design', wh ich eventually grew to 19 R&D projects and one coordination project, with an overall budget of 14 million Euro. It is meanwhile known as European Low Power Initiative for Electronic System Design (ESD-LPD) and will be completed by the end of 2001. It involves 30 major Euro pean companies and 20 well-known institutes. The R&D projects aims to develop or demonstrate new design methods for power reduction, while the coordination project takes care that the methods, experiences and results are properly documented and pub licised."

This book addresses the issue of Machine Learning (ML) attacks on Integrated Circuits through Physical Unclonable Functions (PUFs). It provides the mathematical proofs of the vulnerability of various PUF families, including Arbiter, XOR Arbiter, ring-oscillator, and bistable ring PUFs, to ML attacks. To achieve this goal, it develops a generic framework for the assessment of these PUFs based on two main approaches. First, with regard to the inherent physical characteristics, it establishes fit-for-purpose mathematical representations of the PUFs mentioned above, which adequately reflect the physical behavior of these primitives. To this end, notions and formalizations that are already familiar to the ML theory world are reintroduced in order to give a better understanding of why, how, and to what extent ML attacks against PUFs can be feasible in practice. Second, the book explores polynomial time ML algorithms, which can learn the PUFs under the appropriate representation. More importantly, in contrast to previous ML approaches, the framework presented here ensures not only the accuracy of the model mimicking the behavior of the PUF, but also the delivery of such a model. Besides off-the-shelf ML algorithms, the book applies a set of algorithms hailing from the field of property testing, which can help to evaluate the security of PUFs. They serve as a "toolbox", from which PUF designers and manufacturers can choose the indicators most relevant for their requirements. Last but not least, on the basis of learning theory concepts, the book explicitly states that the PUF families cannot be considered as an ultimate solution to the problem of insecure ICs. As such, it provides essential insights into both academic research on and the design and manufacturing of PUFs.

This book serves as a hands-on guide to RF tunable devices, circuits and subsystems. An innovative of modeling for tunable devices and networks is described, along with a new tuning algorithm, adaptive matching network control approach, and novel filter frequency automatic control loop. The author provides readers with the necessary background and methods for designing and developing tunable RF networks/circuits and tunable RF font-ends, with an emphasis on applications to cellular communications.

The size of technically producible integrated circuits increases continuously, but the ability to design and verify these circuits does not keep up. Therefore today 's design flow has to be improved. Using a visionary approach, this book analyzes the current design methodology and verification methodology, a number of deficiencies are identified and solutions suggested. Improvements in the methodology as well as in the underlying algorithms are proposed.

After long years of work that have seen little industrial application, high-level synthesis is finally on the verge of becoming a practical tool. The state of high-level synthesis today is similar to the state of logic synthesis ten years ago. At present, logic-synthesis tools are widely used in digital system design. In the future, high-level synthesis will play a key role in mastering design complexity and in truly exploiting the potential of ASIes and PLDs, which demand extremely short design cycles. Work on high-level synthesis began over twenty years ago. Since substantial progress has been made in understanding the basic then, problems involved, although no single universally-accepted theoretical framework has yet emerged. There is a growing number of publications devoted to high-level synthesis, specialized workshops are held regularly, and tutorials on the topic are commonly held at major conferences. This book gives an extensive survey of the research and development in high-level synthesis. In Part I, a short tutorial explains the basic concepts used in high-level synthesis, and follows an example design throughout the synthesis process. In Part II, current high-level synthesis systems are surveyed.

Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design discusses new approaches to better timing-closure and manufacturability of DSM Integrated Circuits. The key idea presented is the use of regular circuit and interconnect structures such that area/delay can be predicted with high accuracy. The co-design of structures and algorithms allows great opportunities for achieving better final results, thus closing the gap between IC and CAD designers. The regularities also provide simpler and possibly better manufacturability.
In this book we present not only algorithms for solving particular sub-problems but also systematic ways of organizing different algorithms in a flow to solve the design problem as a whole. A timing-driven chip design flow is developed based on the new structures and their design algorithms, which produces faster chips in a shorter time.

This book describes the design of fully digital multistandard transmitter front-ends which can directly drive one or more switching power amplifiers, thus eliminating all other analog components. After reviewing different architectures, the authors focus on polar architectures using pulse width modulation (PWM), which are entirely based on unclocked delay lines and other continuous-time digital hardware. As a result, readers are enabled to shift accuracy concerns from the voltage domain to the time domain, to coincide with submicron CMOS technology scaling. The authors present different architectural options and compare them, based on their effect on the signal and spectrum quality. Next, a high-level theoretical analysis of two different PWM-based architectures - baseband PWM and RF PWM - is made. On the circuit level, traditional digital components and design techniques are revisited from the point of view of continuous-time digital circuits. Important design criteria are identified and different solutions are presented, along with their advantages and disadvantages. Finally, two chips designed in nanometer CMOS technologies are described, along with measurement results for validation.

Timing research in high performance VLSI systems has advanced at a steady pace over the last few years. Tools, however, especially theoretical mechanisms, lag behind. Much of the present timing research relies heavily on timing diagrams, which although intuitive, are inadequate for analysis of large designs with many parameters. Further, timing diagrams offer only approximations, not exact solutions to many timing problems and provide little insight in the cases where temporal properties of a design interact intricately with the design's logical functionalities. Timed Boolean Functions presents a methodology for timing research which facilitates analysis and design of circuits and systems in a unified temporal and logical domain. The goal of the book is to present the central idea of representing logical and timing information in a common structure, TBFs, and to present a canonical form suitable for efficient manipulation. This methodology is then applied to practical applications to provide intuition and insight into the subject so that these general methods can be adapted to specific engineering problems and also to further the research necessary to enhance the understanding of the field. Timed Boolean Functions is written for professionals involved in timing research and digital designers who want to enhance their understanding of the timing aspects of high speed circuits. The prerequisites are a common background in logic design, computer algorithms, combinatorial optimization and a certain degree of mathematical sophistication.

This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.

The simplest method of transferring data through the inputs or outputs of a silicon chip is to directly connect each bit of the datapath from one chip to the next chip. Once upon a time this was an acceptable approach. However, one aspect (and perhaps the only aspect) of chip design which has not changed during the career of the authors is Moore's Law, which has dictated substantial increases in the number of circuits that can be manufactured on a chip. The pin densities of chip packaging technologies have not increased at the same pace as has silicon density, and this has led to a prevalence of High Speed Serdes (HSS) devices as an inherent part of almost any chip design. HSS devices are the dominant form of input/output for many (if not most) high-integration chips, moving serial data between chips at speeds up to 10 Gbps and beyond. Chip designers with a background in digital logic design tend to view HSS devices as simply complex digital input/output cells. This view ignores the complexity associated with serially moving billions of bits of data per second. At these data rates, the assumptions associated with digital signals break down and analog factors demand consideration. The chip designer who oversimplifies the problem does so at his or her own peril.

too vast, too complex, too grand ... for description. John Wesley Powell-1870 (discovering the Grand Canyon) VHDL is a big world. A beginner can be easily disappointed by the generality of this language. This generality is explained by the large number of domains covered - from specifications to logical simulation or synthesis. To the very beginner, VHDL appears as a "kit". He is quickly aware that his problem may be solved with VHDL, but does not know how. He does not even know how to start. In this state of mind, all the constraints that can be set to his modeling job, by using a subset of the language or a given design methodology, may be seen as a life preserver. The success of the introduction of VHDL in a company depends on solutions to many questions that should be answered months before the first line of code is written: * Why choose VHDL? * Which VHDL tools should be chosen? * Which modeling methodology should be adopted? * How should the VHDL environment be customized? * What are the tricks? Where are the traps? * What are the differences between VHDL and other competing HDLs? Answers to these questions are organized according to different concerns: buying the tools, organizing the environment, and designing. Decisions taken in each of these areas may have many consequences on the way to the acceptance and efficiently use of VHDL in a company.

This comprehensive book deals with feedback and feedback amplifiers, presenting original material on the topic of feedback circuits. After describing the fundamental properties of feedback, the book illustrates techniques of analysis for greater insight into feedback amplifiers and design strategies to optimise their performance.

This book serves a dual purpose: firstly to combine the treatment of circuits and digital electronics, and secondly, to establish a strong connection with the contemporary world of digital systems. The need for this approach arises from the observation that introducing digital electronics through a course in traditional circuit analysis is fast becoming obsolete. Our world has gone digital. Automata theory helps with the design of digital circuits such as parts of computers, telephone systems and control systems. A complete perspective is emphasized, because even the most elegant computer architecture will not function without adequate supporting circuits. The focus is on explaining the real-world implementation of complete digital systems. In doing so, the reader is prepared to immediately begin design and implementation work. This work serves as a bridge to take readers from the theoretical world to the everyday design world where solutions must be complete to be successful.

For more than four decades, the scaling of semiconductor process technologies has revolutionized electronics applications, with complementary metal-oxide-semiconductor (CMOS) technology dominating the semiconductor industry in recent years. The scaling of CMOS technology coupled with advanced in circuits structures and microarchitectures have significantly increased the performance of integrated circuits (ICs). The side-effects of these performance and functional enhancements have traditionally been increased design complexity, greater power consumption, and higher fabrication cost. Multi-voltage design now plays a crucial role in allowing the industry to meet the growing customer demand for high-performance ICs offering a wider variety of applications at a reduced cost.

Multi-voltage CMOS Circuit Design provides an in-depth analysis of several new techniques for designing low-power and high-speed ICs with particular emphasis on the approaches based on using multiple supply and threshold voltages. Starting with a detailed overview of the evolution of IC technologies, the authors go on to examine: the sources of power consumption in CMOS ICs; the mechanism that produce sub-threshold and gate oxide leakage currents; advanced supply and threshold voltage scaling techniques for lowering power consumption and enhancing reliability; energy-efficient monolithic DC-DC conversion techniques for low voltage applications such as microprocessors; in-depth evaluation of the potential of emerging multi-voltage circuit techniques for sustaining the scaling trends of CMOS technologies.

A valuable text for researches and electronic engineers working in the semiconductor technology industry, Multi-voltage CMOS Circuit Design is also a useful reference for graduate students taking courses on advanced topics in IC design.

Traditionally, Computer Aided Design (CAD) tools have been used to create the nominal design of an integrated circuit (IC), such that the circuit nominal response meets the desired performance specifications. In reality, however, due to the disturbances ofthe IC manufacturing process, the actual performancesof the mass produced chips are different than those for the nominal design. Even if the manufacturing process were tightly controlled, so that there were little variations across the chips manufactured, the environmentalchanges (e. g. those oftemperature, supply voltages, etc. ) would alsomakethe circuit performances vary during the circuit life span. Process-related performance variations may lead to low manufacturing yield, and unacceptable product quality. For these reasons, statistical circuit design techniques are required to design the circuit parameters, taking the statistical process variations into account. This book deals with some theoretical and practical aspects of IC statistical design, and emphasizes how they differ from those for discrete circuits. It de scribes a spectrum of different statistical design problems, such as parametric yield optimization, generalized on-target design, variability minimization, per formance tunning, and worst-case design. The main emphasis of the presen tation is placed on the principles and practical solutions for performance vari ability minimization. It is hoped that the book may serve as an introductory reference material for various groups of IC designers, and the methodologies described will help them enhance the circuit quality and manufacturability. The book containsseven chapters."

This book shows readers to avoid common mistakes in circuit design, and presents classic circuit concepts and design approaches from the transistor to the system levels. The discussion is geared to be accessible and optimized for practical designers who want to learn to create circuits without simulations. Topic by topic, the author guides designers to learn the classic analog design skills by understanding the basic electronics principles correctly, and further prepares them to feel confident in designing high-performance, state-of-the art CMOS analog systems. This book combines and presents all in-depth necessary information to perform various design tasks so that readers can grasp essential material, without reading through the entire book. This top-down approach helps readers to build practical design expertise quickly, starting from their understanding of electronics fundamentals.

This book covers the theoretical background, experimental methods and implementation details to engineer for communication and imaging application, terahertz devices using metamaterials, in mainstream semiconductor foundry processes. This book will provide engineers and physicists an authoritative reference to construct such devices with minimal background. The authors describe the design and construction of electromagnetic (EM) devices for terahertz frequencies (108-1010 cycles/sec) using artificial materials that are a fraction of the wavelength of the incident EM wave, resulting in an effective electric and magnetic properties (permittivity and permeability) that are unavailable in natural materials.

This book provides a comprehensive coverage of System-on-Chip (SoC) post-silicon validation and debug challenges and state-of-the-art solutions with contributions from SoC designers, academic researchers as well as SoC verification experts. The readers will get a clear understanding of the existing debug infrastructure and how they can be effectively utilized to verify and debug SoCs.

In recent years the mathematical modeling of charge transport in semi conductors has become a thriving area in applied mathematics. The drift diffusion equations, which constitute the most popular model for the simula tion of the electrical behavior of semiconductor devices, are by now mathe matically quite well understood. As a consequence numerical methods have been developed, which allow for reasonably efficient computer simulations in many cases of practical relevance. Nowadays, research on the drift diffu sion model is of a highly specialized nature. It concentrates on the explora tion of possibly more efficient discretization methods (e.g. mixed finite elements, streamline diffusion), on the improvement of the performance of nonlinear iteration and linear equation solvers, and on three dimensional applications. The ongoing miniaturization of semiconductor devices has prompted a shift of the focus of the modeling research lately, since the drift diffusion model does not account well for charge transport in ultra integrated devices. Extensions of the drift diffusion model (so called hydrodynamic models) are under investigation for the modeling of hot electron effects in submicron MOS-transistors, and supercomputer technology has made it possible to employ kinetic models (semiclassical Boltzmann-Poisson and Wigner Poisson equations) for the simulation of certain highly integrated devices."