This book presents a state of the art review of integrated circuits, systems and transceivers for wireless and mobile communications. Contributions from world-class researchers focus upon the most recent developments in key RF, IF and baseband components and subsystems and transceiver architecture in CMOS technology. Adopting a top-down approach from wireless communications systems, mobile terminals and transceivers, to constituent components, this book covers the whole range of baseband, IF and RF issues in a systematic way. Circuit and system techniques for design and implementation of reconfigurable low voltage and low power single-chip CMOS transceivers for both mobile cellular and wireless LAN applications are included.

This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems. It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time. Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today's multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifying problems and solutions. She then describes out-of-order parallel discrete event simulation (OoO PDES), a novel approach for efficient validation of system-level designs by aggressively exploiting the parallel capabilities of todays' multi-core PCs. This approach enables readers to design simulators that can fully exploit the parallel processing capability of the multi-core system to achieve fast speed simulation, without loss of simulation and timing accuracy. Based on this parallel simulation infrastructure, the author further describes automatic approaches that help the designer quickly to narrow down the debugging targets in faulty ESL models with parallelism.

This book introduces a new cyberphysical system that combines clinical and basic neuroscience research with advanced data analysis and medical management tools for developing novel applications for the management of epilepsy. The authors describe the algorithms and architectures needed to provide ambulatory, diagnostic and long-term monitoring services, through multi parametric data collection. Readers will see how to achieve in-hospital quality standards, addressing conventional "routine" clinic-based service purposes, at reduced cost, enhanced capability and increased geographical availability. The cyberphysical system described in this book is flexible, can be optimized for each patient and is demonstrated in several case studies.

This first book on load-pull systems is intended for readers with a broad knowledge of high frequency transistor device characterization, nonlinear and linear microwave measurements, RF power amplifiers and transmitters. Load-Pull Techniques with Applications to Power Amplifier Design fulfills the demands of users, designers, and researchers both from industry and academia who have felt the need of a book on this topic. It presents a comprehensive reference spanning different load-pull measurement systems, waveform measurement and engineering systems, and associated calibration procedures for accurate large signal characterization. Besides, this book also provides in-depth practical considerations required in the realization and usage of load-pull and waveform engineering systems. In addition, it also provides procedure to design application specific load-pull setup and includes several case studies where the user can customize architecture of load-pull setups to meet any specific measurement requirements. Furthermore, the materials covered in this book can be part of a full semester graduate course on microwave device characterization and power amplifier design.

This book presents exact, that is minimal, solutions to individual steps in the design process for Digital Microfluidic Biochips (DMFBs), as well as a one-pass approach that combines all these steps in a single process. All of the approaches discussed are based on a formal model that can easily be extended to cope with further design problems. In addition to the exact methods, heuristic approaches are provided and the complexity classes of various design problems are determined. Presents exact methods to tackle a variety of design problems for Digital Microfluidic Biochips (DMFBs); Describes an holistic, one-pass approach solving different design steps all at once; Based on a formal model of DMFBs that is easily adaptable to deal with further design tasks.

This book provides a single-source reference on the use of carbon nanotubes (CNTs) as interconnect material for horizontal, on-chip and 3D interconnects. The authors demonstrate the uses of bundles of CNTs, as innovative conducting material to fabricate interconnect through-silicon vias (TSVs), in order to improve the performance, reliability and integration of 3D integrated circuits (ICs). This book will be first to provide a coherent overview of exploiting carbon nanotubes for 3D interconnects covering aspects from processing, modeling, simulation, characterization and applications. Coverage also includes a thorough presentation of the application of CNTs as horizontal on-chip interconnects which can potentially revolutionize the nanoelectronics industry. This book is a must-read for anyone interested in the state-of-the-art on exploiting carbon nanotubes for interconnects for both 2D and 3D integrated circuits.

With the proliferation of VHDL, the reference material also grew in the same order. Today there is good amount of scholarly literature including many books describing various aspects of VHDL. However, an indepth review of these books reveals a different story. Many of them have emerged simply as an improved version of the manual. While some of them deal with the system design issues, they lack appropriate exemplifying to illustrate the concepts. Others give large number of examples, but lack the VLSI system design issues.

In nutshell, the fact which gone unnoticed by most of the books, is the growth of the VLSI is not merely due to the language itself, but more due to the development of large number of third party tools useful from the FPGA or semicustom ASIC realization point of view. In the proposed book, the authors have synergized the VHDL programming with appropriate EDA tools so as to present a full proof system design to the readers. In this book along with the VHDL coding issues, the simulation and synthesis with the various toolsets enables the potential reader to visualize the final design. The VHDL design codes have been synthesized using different third party tools such as Xilinx Web pack Ver.11, Modelsim PE, Leonrado Spectrum and Synplify Pro. Mixed flow illustrated by using the above mentioned tools presents an insight to optimize the design with reference to the spatial, temporal and power metrics.

Embedded systems have been almost invisibly pervading our daily lives for several decades. They facilitate smooth operations in avionics, automotive electronics, or telecommunication. New problems arise by the increasing employment, interconnection, and communication of embedded systems in heterogeneous environments: How secure are these embedded systems against attacks or breakdowns? Therefore, how can embedded systems be designed to be more secure? How can embedded systems autonomically react to threats? Facing these questions, Sorin A. Huss is significantly involved in the exploration of design methodologies for secure embedded systems. This Festschrift is dedicated to him and his research on the occasion of his 60th birthday.

Traditionally, design space exploration for Systems-on-Chip (SoCs) has focused on the computational aspects of the problem at hand. However, as the number of components on a single chip and their performance continue to increase, the communication architecture plays a major role in the area, performance and energy consumption of the overall system. As a result, a shift from computation-based to communication-based design becomes mandatory. Towards this end, network-on-chip (NoC) communication architectures have emerged recently as a promising alternative to classical bus and point-to-point communication architectures.

In this dissertation, we study outstanding research problems related to modeling, analysis and optimization of NoC communication architectures. More precisely, we present novel design methodologies, software tools and FPGA prototypes to aid the design of application-specific NoCs.

This book describes new, fuzzy logic-based mathematical apparatus, which enable readers to work with continuous variables, while implementing whole circuit simulations with speed, similar to gate-level simulators and accuracy, similar to circuit-level simulators. The author demonstrates newly developed principles of digital integrated circuit simulation and optimization that take into consideration various external and internal destabilizing factors, influencing the operation of digital ICs. The discussion includes factors including radiation, ambient temperature, electromagnetic fields, and climatic conditions, as well as non-ideality of interconnects and power rails.

Computerarchitecturepresentlyfacesanunprecedentedrevolution: Thestep from monolithic processors towards multi-core ICs, motivated by the ever - creasingneedforpowerandenergyef ciencyinnanoelectronics. Whetheryou prefer to call it MPSoC (multi-processor system-on-chip) or CMP (chip mul- processor), no doubt this revolution affects large domains of both computer science and electronics, and it poses many new interdisciplinary challenges. For instance, ef cient programming models and tools for MPSoC are largely an open issue: "Multi-core platforms are a reality - but where is the software support" (R. Lauwereins, IMEC). Solving it will require enormous research efforts as well as the education of a whole new breed of software engineers that bring the results from universities into industrial practice. Atthesametime, thedesignofcomplexMPSoCarchitecturesisanextremely time-consuming task, particularly in the wireless and multimedia application domains, where heterogeneous architectures are predominant. Due to the - ploding NRE and mask costs most companies are now following a platform approach: Invest a large (but one-time) design effort into a proper core - chitecture, and create easy-to-design derivatives for new standards or product features. Needless to say, only the most ef cient MPSoC platforms have a real chance to enjoy a multi-year lifetime on the highly competitive semiconductor market for embedded systems.

From the reviews: " ...] a welcome addition to the literature. ...] This book promises to make a valuable contribution to the education of graduate students in electrical and computer engineering, and a very useful addition to the library of the maturer investigator in SoC designs or related fields." Microelectronics Reliability

Kinetic energy harvesting converts movement or vibrations into electrical energy, enables battery free operation of wireless sensors and autonomous devices and facilitates their placement in locations where replacing a battery is not feasible or attractive. This book provides an introduction to operating principles and design methods of modern kinetic energy harvesting systems and explains the implications of harvested power on autonomous electronic systems design. It describes power conditioning circuits that maximize available energy and electronic systems design strategies that minimize power consumption and enable operation. The principles discussed in the book will be supported by real case studies such as battery-less monitoring sensors at water waste processing plants, embedded battery-less sensors in automotive electronics and sensor-networks built with ultra-low power wireless nodes suitable for battery-less applications.

Analog design is one of the more difficult aspects of electrical engineering. The main reason is the apparently vague decisions an experienced designer makes in optimizing his circuit. To enable fresh designers, like students electrical engineering, to become acquainted with analog circuit design, structuring the analog design process is of utmost importance.
Structured Electronic Design: Negative-Feedback Amplifiers presents a design methodology for negative-feedback amplifiers. The design methodology enables to synthesize a topology and to, at the same time, optimize the performance of that topology.
Key issues in the design methodology are orthogonalization, hierarchy and simple models. Orthogonalization enables the separate optimization of the three fundamental quality aspects: noise, distortion and bandwidth. Hierarchy ensures that the right decisions are made at the correct level of abstraction. The use of simple models, results in simple calculations yielding maximum-performance indicators that can be used to reject wrong circuits relatively fast.
The presented design methodology divides the design of negative-feedback amplifiers in six independent steps. In the first two steps, the feedback network is designed. During those design steps, the active part is assumed to be a nullor, i.e. the performance with respect to noise, distortion and bandwidth is still ideal.
In the subsequent four steps, an implementation for the active part is synthesized. During those four steps the topology of the active part is synthesized such that optimum performance is obtained. Firstly, the input stage is designed with respect to noise performance. Secondly, the output stage isdesigned with respect to clipping distortion. Thirdly, the bandwidth performance is designed, which may require the addition of an additional amplifying stage. Finally, the biasing circuitry for biasing the amplifying stages is designed.
By dividing the design in independent design steps, the total global optimization is reduced to several local optimizations. By the specific sequence of the design steps, it is assured that the local optimizations yield a circuit that is close to the global optimum. On top of that, because of the separate dedicated optimizations, the resource use, like power, is tracked clearly.
Structured Electronic Design: Negative-Feedback Amplifiers presents in two chapters the background and an overview of the design methodology. Whereafter, in six chapters the separate design steps are treated with great detail. Each chapter comprises several exercises. An additional chapter is dedicated to how to design current sources and voltage source, which are required for the biasing. The final chapter in the book is dedicated to a thoroughly described design example, showing clearly the benefits of the design methodology.
In short, this book is valuable for M.Sc.-curriculum Electrical Engineering students, and of course, for researchers and designers who want to structure their knowledge about analog design further.

Lead-free solders are used extensively as interconnection materials in electronic assemblies and play a critical role in the global semiconductor packaging and electronics manufacturing industry. Electronic products such as smart phones, notebooks and high performance computers rely on lead-free solder joints to connect IC chip components to printed circuit boards." Lead Free Solder: Mechanics and Reliability" provides in-depth design knowledge on lead-free solder elastic-plastic-creep and strain-rate dependent deformation behavior and its application in failure assessment of solder joint reliability. It includes coverage of advanced mechanics of materials theory and experiments, mechanical properties of solder and solder joint specimens, constitutive models for solder deformation behavior; numerical modeling and simulation of solder joint failure subject to thermal cycling, mechanical bending fatigue, vibration fatigue and board-level drop impact tests.

In the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation.

Automatic Performance Tuning is a new software paradigm which enables software to be high performance in any computing environment. Its methodologies have been developed over the past decade, and it is now rapidly growing in terms of its scope and applicability, as well as in its scientific knowledge and technological methods. Software developers and researchers in the area of scientific and technical computing, high performance database systems, optimized compilers, high performance systems software, and low-power computing will find this book to be an invaluable reference to this powerful new paradigm.

This self-contained book addresses the need for analysis, characterization, estimation, and optimization of the various forms of power dissipation in the presence of process variations of nano-CMOS technologies. The authors show very large-scale integration (VLSI) researchers and engineers how to minimize the different types of power consumption of digital circuits. The material deals primarily with high-level (architectural or behavioral) energy dissipation.

This book presents the a scientific discussion of the state-of-the-art techniques and designs for modeling, testing and for the performance analysis of data converters. The focus is put on sustainable data conversion. Sustainability has become a public issue that industries and users can not ignore. Devising environmentally friendly solutions for data conversion designing, modeling and testing is nowadays a requirement that researchers and practitioners must consider in their activities. This book presents the outcome of the IWADC workshop 2011, held in Orvieto, Italy.

This book addresses reliability and energy efficiency of on-chip networks using cooperative error control. It describes an efficient way to construct an adaptive error control codec capable of tracking noise conditions and adjusting the error correction strength at runtime. Methods are also presented to tackle joint transient and permanent error correction, exploiting the redundant resources already available on-chip. A parallel and flexible network simulator is also introduced, which facilitates examining the impact of various error control methods on network-on-chip performance.

This book covers state-of-the art techniques for high-level modeling and validation of complex hardware/software systems, including those with multicore architectures. Readers will learn to avoid time-consuming and error-prone validation from the comprehensive coverage of system-level validation, including high-level modeling of designs and faults, automated generation of directed tests, and efficient validation methodology using directed tests and assertions. The methodologies described in this book will help designers to improve the quality of their validation, performing as much validation as possible in the early stages of the design, while reducing the overall validation effort and cost.

Organic and printed electronics can enable a revolution in the applications of electronics and this book offers readers an overview of the state-of-the-art in this rapidly evolving domain. The potentially low cost, compatibility with flexible substrates and the wealth of devices that characterize organic and printed electronics will make possible applications that go far beyond the well-known displays made with large-area silicon electronics. Since organic electronics are still in their early stage, undergoing transition from lab-scale and prototype activities to production, this book serves as a valuable snapshot of the current landscape of the different devices enabled by this technology, reviewing all applications that are developing and those can be foreseen. "

This book describes the current state of the art in big-data analytics, from a technology and hardware architecture perspective. The presentation is designed to be accessible to a broad audience, with general knowledge of hardware design and some interest in big-data analytics. Coverage includes emerging technology and devices for data-analytics, circuit design for data-analytics, and architecture and algorithms to support data-analytics. Readers will benefit from the realistic context used by the authors, which demonstrates what works, what doesn’t work, and what are the fundamental problems, solutions, upcoming challenges and opportunities. Provides a single-source reference to hardware architectures for big-data analytics; Covers various levels of big-data analytics hardware design abstraction and flow, from device, to circuits and systems; Demonstrates how non-volatile memory (NVM) based hardware platforms can be a viable solution to existing challenges in hardware architecture for big-data analytics.

Great strides have been made in the development of analog filters over thepast few decades. The first book to treat these recent advancesin depth, "VLSI Analog Filters" provides a comprehensive guide for researchers and upper-level graduate students, whichfully preparesreaders for professional work. In particular, the work covers active R filters, OTA-C filters, and switched-capacitor filters, including topics such as differential output opamps, sensitivity analysis for passive components, multiple-feedback techniques, double-sampling, and N-path filters. Throughout the book, exercises are included to reinforce understanding of concepts, and simulations are used to enhance connections to practical applications.

This advanced textbook is suitable for engineeringgraduate students studying analog filter design, offering a full course that can feed seamlessly toemployment industry. At the same time, it serves asan extremely valuable referencefor researchers and engineerslooking to gain a deeper understanding of the field."

This book considers the design and development of nanoelectronic computing circuits, systems and architectures focusing particularly on memristors, which represent one of today's latest technology breakthroughs in nanoelectronics. The book studies, explores, and addresses the related challenges and proposes solutions for the smooth transition from conventional circuit technologies to emerging computing memristive nanotechnologies. Its content spans from fundamental device modeling to emerging storage system architectures and novel circuit design methodologies, targeting advanced non-conventional analog/digital massively parallel computational structures. Several new results on memristor modeling, memristive interconnections, logic circuit design, memory circuit architectures, computer arithmetic systems, simulation software tools, and applications of memristors in computing are presented. High-density memristive data storage combined with memristive circuit-design paradigms and computational tools applied to solve NP-hard artificial intelligence problems, as well as memristive arithmetic-logic units, certainly pave the way for a very promising memristive era in future electronic systems. Furthermore, these graph-based NP-hard problems are solved on memristive networks, and coupled with Cellular Automata (CA)-inspired computational schemes that enable computation within memory. All chapters are written in an accessible manner and are lavishly illustrated. The book constitutes an informative cornerstone for young scientists and a comprehensive reference to the experienced reader, hoping to stimulate further research on memristive devices, circuits, and systems.