"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks."
- Stuart Swan

With the increased efforts of the analog design community to integrate analog high-frequency front-ends for telecommunications, there has been heightened interest in the behaviour of nonlinear circuits since this can cause considerable degradation of signals. In analog integrated circuits at lower frequencies, such as filters, nonlinear behaviour limits the dynamic range. Analog integrated circuit designers often lack insight into nonlinear circuit behaviour. Indeed, designers are trained to reason in linear or linearized circuits but not in nonlinear ones. Numerical circuit simulations of nonlinear circuit behavior do not provide enough insight to the designer. Distortion Analysis of Analog Integrated Circuits, with a foreword by Robert G. Meyer, provides both qualitative and quantitative insight into the nonlinear behavior of analog integrated circuits at low and high frequencies. General techniques to suppress nonlinear behavior such as pre-distortion, linear and nonlinear feedback are explained in detail and illustrated with realistic examples. In this way the book fills the gap between the theory of nonlinear systems and practical analog integrated circuits. Distortion Analysis of Analog Integrated Circuits provides the reader with an in-depth analysis of elementary transistor stages, both CMOS and bipolar, as well as an analysis of several larger circuits. Hereby use is made of advanced transistor models that are also discussed in the book. The analyses take into account many more effects than in existing publications, thanks to the use of a calculation method that yields closed-form expressions for nonlinear behavior. These expressions are interpreted and illustrated withrealistic numerical examples. Distortion Analysis of Analog Integrated Circuits is essential reading for practicing analog and mixed-signal design engineers and researchers in the field. It is also suitable as a text for an advanced course on the subject. From the foreword: I am sure that the analog circuit design community will [...] welcome this work by Dr. Wambacq and Prof. Sansen as a major contribution to the analog circuit design literature in the area of distortion analysis of electronic circuits. I am personally looking forward to having a copy readily available for reference when designing integrated circuits for communication systems.' Robert G. Meyer, Professor, Electrical Engineering and Computer Sciences, University of California, Berkeley.

Explains how to use low power design in an automated design flow, and examine the design time and performance trade-offs

Includes the latest tools and techniques for low power design applied in an ASIC design flow

Focuses on low power in an automated design methodology, a much neglected area

Written by an author with extensive practical experience of applying the techniques, this book is aimed at advanced students and researchers as well as professional design engineers. The text focuses on finite impulse response (FIR) filter structures and on infinite impulse response (IIR) SC filters which simulate classical lossless circuits . It includes coverage of the so-called pseudo-lossless SC circuits and especially multirate SC circuits with recovery of the effective pseudo-energy. There is also discussion of other promising approaches to the design of SC circuits; special attention has been paid to the analysis of multirate and multiphase SC circuits using signal flow graphs.

High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components.

Provides coverage of the most efficient and effective methods of network analysis optimization and synthesis. A step-by-step guide to every aspect of the RF and microwave circuit design process - starting with a set of specifications and ending with hardware that performs as modeled the first time.

Digital phase locked loops are critical components of many communication, signal processing and control systems. This exciting new book covers various types of digital phase lock loops. It presents a comprehensive coverage of a new class of digital phase lock loops called the time delay tanlock loop (TDTL). It also details a number of architectures that improve the performance of the TDTL through adaptive techniques that overcome the conflicting requirements of the locking rage and speed of acquisition. These requirements are of paramount importance in many applications including wireless communications, consumer electronics and others. Digital Phase Lock Loops then illustrates the process of converting the TDTL class of digital phase lock loops for implementation on an FPGA-based reconfigurable system. These devices are being utilized in software-defined radio, DSP-based designs and many other communication and electronic systems to implement complex high-speed algorithms. Their flexibility and reconfigurability facilitate rapid prototyping, on-the-fly upgradeability, and code reuse with minimum effort and complexity. from the reconfigurable implementations are compared with those obtained through simulations with MATLAB/Simulink. The material in this book will be valuable to researchers, graduate students, and practicing engineers.

Debugging becomes more and more the bottleneck to chip design productivity, especially while developing modern complex integrated circuits and systems at the Electronic System Level (ESL). Today, debugging is still an unsystematic and lengthy process. Here, a simple reporting of a failure is not enough, anymore. Rather, it becomes more and more important not only to find many errors early during development but also to provide efficient methods for their isolation. In Debugging at the Electronic System Level the state-of-the-art of modeling and verification of ESL designs is reviewed. There, a particular focus is taken onto SystemC. Then, a reasoning hierarchy is introduced. The hierarchy combines well-known debugging techniques with whole new techniques to improve the verification efficiency at ESL. The proposed systematic debugging approach is supported amongst others by static code analysis, debug patterns, dynamic program slicing, design visualization, property generation, and automatic failure isolation. All techniques were empirically evaluated using real-world industrial designs. Summarized, the introduced approach enables a systematic search for errors in ESL designs. Here, the debugging techniques improve and accelerate error detection, observation, and isolation as well as design understanding.

Device and Circuit Cryogenic Operation for Low Temperature Electronics is a first in reviewing the performance and physical mechanisms of advanced devices and circuits at cryogenic temperatures that can be used for many applications. The first two chapters cover bulk silicon and SOI MOSFETs. The electronic transport in the inversion layer, the influence of impurity freeze-out, the special electrical properties of SOI structures, the device reliability and the interest of a low temperature operation for the ultimate integration of silicon down to nanometer dimensions are described. The next two chapters deal with Silicon-Germanium and III-V Heterojunction Bipolar Transistors, as well as III-V High Electron Mobility Transistors (HEMT). The basic physics of the SiGe HBT and its unique cryogenic capabilities, the optimization of such bipolar devices, and the performance of SiGe HBT BiCMOS technology at liquid nitrogen temperature are examined. The physical effects in III-V semiconductors at low temperature, the HEMT and HBT static, high frequency and noise properties, and the comparison of various cooled III-V devices are also addressed. The next chapter treats quantum effect devices made of silicon materials. The major quantum effects at low temperature, quantum wires, quantum dots as well as single electron devices and applications are investigated. The last chapter overviews the performances of cryogenic circuits and their applications. The low temperature properties and performance of inverters, multipliers, adders, operational amplifiers, memories, microprocessors, imaging devices, circuits and systems, sensors and read-out circuits are analyzed. Device and Circuit Cryogenic Operation for Low Temperature Electronics is useful for researchers, engineers, Ph.D. and M.S. students working in the field of advanced electron devices and circuits, new semiconductor materials, and low temperature electronics and physics.

Conceptual Design of Multichip Modules and Systems treats activities which take place at the conceptual and specification level of the design of complex multichip systems. These activities include the formalization of design knowledge (information modeling), tradeoff analysis, partitioning, and decision process capture. All of these functions occur prior to the traditional CAD activities of synthesis and physical design. Inherent in the design of electronic modules are tradeoffs which must be understood before feasible technology, material, process, and partitioning choices can be selected. The lack of a complete set of technology information is an especially serious problem in the packaging and interconnect field since the number of technologies, process, and materials is substantial and selecting optimums is arduous and non-trivial if one truly wants a balance in cost and performance. Numerous tradeoff and design decisions have to be made intelligently and quickly at the beginning of the design cycle before physical design work begins. These critical decisions, made within the first 10% of the total design cycle, ultimately define up to 80% of the final product cost. Conceptual Design of Multichip Modules and Systems lays the groundwork for concurrent estimation level analysis including size, routing, electrical performance, thermal performance, cost, reliability, manufacturability, and testing. It will be useful both as a reference for system designers and as a text for those wishing to gain a perspective on the nature of packaging and interconnect design, concurrent engineering, computer-aided design, and system synthesis.

Chemical mechanical planarization, or chemical mechanical polishing as it is simultaneously referred to, has emerged as one of the critical processes in semiconductor manufacturing and in the production of other related products and devices, MEMS for example. Since its introduction some 15+ years ago CMP, as it is commonly called, has moved steadily into new and challenging areas of semiconductor fabrication. Demands on it for consistent, efficient and cost-effective processing have been steady. This has continued in the face of steadily decreasing feature sizes, impressive increases in wafer size and a continuing array of new materials used in devices today. There are a number of excellent existing references and monographs on CMP in circulation and we defer to them for detailed background information. They are cited in the text. Our focus here is on the important area of process mod els which have not kept pace with the tremendous expansion of applications of CMP. Preston's equation is a valuable start but represents none of the subtleties of the process. Specifically, we refer to the development of models with sufficient detail to allow the evaluation and tradeoff of process inputs and parameters to assess impact on quality or quantity of production. We call that an "integrated model" and, more specifically, we include the important role of the mechanical elements of the process."

This book gives a comprehensive introduction to the design challenges of MPSoC platforms, focusing on early design space exploration. It defines an iterative methodology to increase the abstraction level so that evaluation of design decisions can be performed earlier in the design process. These techniques enable exploration on the system level before undertaking time- and cost-intensive development.

This book introduces advanced thyristor-based shunt hybrid active power filters (HAPFs) for power quality improvement in power grids, which are characterized by a low dc-link operating voltage and a wide compensation range. This means they can overcome the high dc-link voltage requirement of conventional active power filters and the narrow compensation range problem of LC-coupling hybrid active power filters. Consisting of 10 chapters, the book discusses the principle, design, control and hardware implementation of thyristor-based hybrid active power filters. It covers 1) V-I characteristics, cost analysis, power loss and reliability studies of different power filters; 2) mitigation of the harmonic injection technique for thyristor-controlled parts; 3) nonlinear pulse width modulation (PWM) control; 4) parameter design methods; 5) minimum inverter capacity design; 6) adaptive dc-link voltage control; 7) unbalanced control strategy; 8) selective compensation techniques; and 9) the hardware prototype design of thyristor-based HAPFs, verified by simulation and experimental results. It enables readers to gain an understanding of the basic power electronics techniques applied in power systems as well as the advanced techniques for controlling, implementing and designing advanced thyristor-based HAPFs.

Variability is one of the most challenging obstacles for IC design in the nanometer regime. In nanometer technologies, SRAM show an increased sensitivity to process variations due to low-voltage operation requirements, which are aggravated by the strong demand for lower power consumption and cost, while achieving higher performance and density. With the drastic increase in memory densities, lower supply voltages, and higher variations, statistical simulation methodologies become imperative to estimate memory yield and optimize performance and power. This book is an invaluable reference on robust SRAM circuits and statistical design methodologies for researchers and practicing engineers in the field of memory design. It combines state of the art circuit techniques and statistical methodologies to optimize SRAM performance and yield in nanometer technologies. Provides comprehensive review of state-of-the-art, variation-tolerant SRAM circuit techniques; Discusses Impact of device related process variations and how they affect circuit and system performance, from a design point of view; Helps designers optimize memory yield, with practical statistical design methodologies and yield estimation techniques.

Over the past decade there has been a dramatic change in the role played by design automation for electronic systems. Ten years ago, integrated circuit (IC) designers were content to use the computer for circuit, logic, and limited amounts of high-level simulation, as well as for capturing the digitized mask layouts used for IC manufacture. The tools were only aids to design-the designer could always find a way to implement the chip or board manually if the tools failed or if they did not give acceptable results. Today, however, design technology plays an indispensable role in the design ofelectronic systems and is critical to achieving time-to-market, cost, and performance targets. In less than ten years, designers have come to rely on automatic or semi automatic CAD systems for the physical design ofcomplex ICs containing over a million transistors. In the past three years, practical logic synthesis systems that take into account both cost and performance have become a commercial reality and many designers have already relinquished control ofthe logic netlist level of design to automatic computer aids. To date, only in certain well-defined areas, especially digital signal process ing and telecommunications. have higher-level design methods and tools found significant success. However, the forces of time-to-market and growing system complexity will demand the broad-based adoption of high-level, automated methods and tools over the next few years."

As embedded systems become more complex, designers face a number of challenges at different levels: they need to boost performance, while keeping energy consumption as low as possible, they need to reuse existent software code, and at the same time they need to take advantage of the extra logic available in the chip, represented by multiple processors working together. This book describes several strategies to achieve such different and interrelated goals, by the use of adaptability. Coverage includes reconfigurable systems, dynamic optimization techniques such as binary translation and trace reuse, new memory architectures including homogeneous and heterogeneous multiprocessor systems, communication issues and NOCs, fault tolerance against fabrication defects and soft errors, and finally, how one can combine several of these techniques together to achieve higher levels of performance and adaptability. The discussion also includes how to employ specialized software to improve this new adaptive system, and how this new kind of software must be designed and programmed.

Dynamic power management is a design methodology aiming at controlling performance and power levels of digital circuits and systems, with the goal of extending the autonomous operation time of battery-powered systems, providing graceful performance degradation when supply energy is limited, and adapting power dissipation to satisfy environmental constraints. Dynamic Power Management: Design Techniques and CAD Tools addresses design techniques and computer-aided design solutions for power management. Different approaches are presented and organized in an order related to their applicability to control-units, macro-blocks, digital circuits and electronic systems, respectively. All approaches are based on the principle of exploiting idleness of circuits, systems, or portions thereof. They involve both the detection of idleness conditions and the freezing of power-consuming activities in the idle components. The book also describes some approaches to system-level power management, including Microsoft's OnNow architecture and the Advanced Configuration and Power Management' standard proposed by Intel, Microsoft and Toshiba. These approaches migrate power management to the software layer running on hardware platforms, thus providing a flexible and self-configurable solution to adapting the power/performance tradeoff to the needs of mobile (and fixed) computing and communication. Dynamic Power Management: Design Techniques and CAD Tools is of interest to researchers and developers of computer-aided design tools for integrated circuits and systems, as well as to system designers.

This book describes several methods and systems solving one of the highlighted problems within computer aided design, namely architectural and logic synthesis. The book emphasises the most recent technologies in high level synthesis, concentrating on applicative studies and practical constraints or criteria during synthesis. Logic and Architecture Synthesis concentrates on the practical problems involving automatic synthesis of designs. It is essential reading for researchers and CAD Managers working in this area.

As integrated circuit (IC) feature sizes scaled below a quarter of a micron, thereby defining the deep submicron (DSM) era, there began a gradual shift in the impact on performance due to the metal interconnections among the active circuit components. Once viewed as merely parasitics in terms of their relevance to the overall circuit behavior, the interconnect can now have a dominant impact on the IC area and performance. Beginning in the late 1980's there was significant research toward better modeling and characterization of the resistance, capacitance and ultimately the inductance of on-chip interconnect. IC Interconnect Analysis covers the state-of-the-art methods for modeling and analyzing IC interconnect based on the past fifteen years of research. This is done at a level suitable for most practitioners who work in the semiconductor and electronic design automation fields, but also includes significant depth for the research professionals who will ultimately extend this work into other areas and applications. IC Interconnect Analysis begins with an in-depth coverage of delay metrics, including the ubiquitous Elmore delay and its many variations. This is followed by an outline of moment matching methods, calculating moments efficiently, and Krylov subspace methods for model order reduction. The final two chapters describe how to interface these reduced-order models to circuit simulators and gate-level timing analyzers respectively. IC Interconnect Analysis is written for CAD tool developers, IC designers and graduate students.

This text is about methods used for the computer simulation of analog systems. It concentrates on electronic applications, but many of the methods are applicable to other engineering problems as well. This revised edition (1st, 1983) encompasses recent theoretical developments and program-writing ti

Photovoltaic generation is one of the cleanest forms of energy conversion available. One of the advantages offered by solar energy is its potential to provide sustainable electricity in areas not served by the conventional power grid. Optimisation of Photovoltaic Power Systems details explicit modelling, control and optimisation of the most popular stand-alone applications such as pumping, power supply, and desalination. Each section is concluded by an example using the MATLAB (R) and Simulink (R) packages to help the reader understand and evaluate the performance of different photovoltaic systems. Optimisation of Photovoltaic Power Systems provides engineers, graduate and postgraduate students with the means to understand, assess and develop their own photovoltaic systems. As such, it is an essential tool for all those wishing to specialise in stand-alone photovoltaic systems. Optimisation of Photovoltaic Power Systems aims to enable all researchers in the field of electrical engineering to thoroughly understand the concepts of photovoltaic systems; find solutions to their problems; and choose the appropriate mathematical model for optimising photovoltaic energy.

"Memory Mass Storage" describes the fundamental storage technologies, like Semiconductor, Magnetic, Optical and Uncommon, detailing the main technical characteristics of the storage devices. It deals not only with semiconductor and hard disk memory, but also with different ways to manufacture and assembly them, and with their application to meet market requirements. It also provides an

introduction to the epistemological issues arising in defining the process of remembering, as well as an overview on human memory,

and an interesting excursus about biological memories and their organization, to better understand how the best memory we have, our brain, is able to imagine and design memory."

Graphene has emerged as a potential candidate to replace traditional CMOS for a number of electronic applications; this book presents the latest advances in graphene nanoelectronics and the potential benefits of using graphene in a wide variety of electronic applications. The book also provides details on various methods to grow graphene, including epitaxial, CVD, and chemical methods. This book serves as a spring-board for anyone trying to start working on graphene. The book is also suitable to experts who wish to update themselves with the latest findings in the field.

This book presents a new optimization flow for quantum circuits realization. At the reversible level, optimization algorithms are presented to reduce the quantum cost. Then, new mapping approaches to decompose reversible circuits to quantum circuits using different quantum libraries are described. Finally, optimization techniques to reduce the quantum cost or the delay are applied to the resulting quantum circuits. Furthermore, this book studies the complexity of reversible circuits and quantum circuits from a theoretical perspective.

This book includes a set of rigorously reviewed world-class manuscripts addressing and detailing state-of-the-art research projects in the areas of Engineering Education, Instructional Technology, Assessment, and E-learning.

The book presents selected papers form the conference proceedings of the International Conference on Engineering Education, Instructional Technology, Assessment, and E-learning (EIAE 2006). All aspects of the conference were managed on-line.