This book is the second of two volumes addressing the design challenges associated with new generations of semiconductor technology. The various chapters are compiled from tutorials presented at workshops in recent years by prominent authors from all over the world. Technology, productivity and quality are the main aspects under consideration to establish the major requirements for the design and test of upcoming systems on a chip.

This book describes a new type of passive electronic components, called fractal elements, from a theoretical and practical point of view. The authors discuss in detail the physical implementation and design of fractal devices for application in fractional-order signal processing and systems. The concepts of fractals and fractal signals are explained, as well as the fundamentals of fractional calculus. Several implementations of fractional impedances are discussed, along with comparison of their performance characteristics. Details of design, schematics, fundamental techniques and implementation of RC-based fractal elements are provided.

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.
This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.
KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

Power consumption becomes the most important design goal in a wide range of electronic systems. There are two driving forces towards this trend: continuing device scaling and ever increasing demand of higher computing power. First, device scaling continues to satisfy Moore's law via a conventional way of scaling (More Moore) and a new way of exploiting the vertical integration (More than Moore). Second, mobile and IT convergence requires more computing power on the silicon chip than ever. Cell phones are now evolving towards mobile PC. PCs and data centers are becoming commodities in house and a must in industry. Both supply enabled by device scaling and demand triggered by the convergence trend realize more computation on chip (via multi-core, integration of diverse functionalities on mobile SoCs, etc.) and finally more power consumption incurring power-related issues and constraints.

"Energy-Aware System Design: Algorithms and Architectures" provides state-of-the-art ideas for low power design methods from circuit, architecture to software level andoffers design case studies in three fast growing areas of mobile storage, biomedical and security.

Important topics and features:

- Describes very recent advanced issues and methods for energy-aware design at each design level from circuit andarchitecture toalgorithm level, and also covering important blocks including low power main memory subsystem and on-chip network at architecture level

- Explains efficient power conversion and delivery which is becoming important as heterogeneous power sources are adopted for digital and non-digital parts

- Investigates 3D die stacking emphasizing temperature awareness for better perspective on energy efficiency

- Presents three practical energy-aware design case studies; novel storage device (e.g., solid state disk), biomedical electronics (e.g., cochlear and retina implants), and wireless surveillance camera systems.

Researchers and engineers in the field of hardware and software design will find this book an excellent starting point to catch up with the state-of-the-art ideas of low power design.

Nanorobots represent a nanoscale device where proteins such as DNA, carbon nanotubes could act as motors, mechanical joints, transmission elements, or sensors. When these different components were assembled together they can form nanorobots with multi-degree-of-freedom, able to apply forces and manipulate objects in the nanoscale world. Design, Modeling and Characterization of Bio-Nanorobotic Systems investigates the design, assembly, simulation, and prototyping of biological and artificial molecular structures with the goal of implementing their internal nanoscale movements within nanorobotic systems in an optimized manner.

Analog Circuit Design contains the contribution of 18 tutorials of the 18th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 18 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of: Smart Data Converters: Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology, Filters on Chip: Chaired by Herman Casier, AMI Semiconductor Fellow, Multimode Transmitters: Chaired by Prof. M. Steyaert, Catholic University Leuven, Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design.

This book describes a new way to design and utilize Instrumentation Amplifiers (IAs) by taking advantages of the current-mode (CM) approach. For the first time, all different topologies of CMIAs are discussed and compared, providing a single-source reference for instrumentation and measurement experts who want to choose a topology for a specific application. The authors also explain major challenges in designing CMIAs, so the book can be useful for anyone studying instrumentation amplifiers, and even other analog circuits. Coverage also includes various CM signal processing techniques employed in CMIAs, and applications of the CMIAs in biomedical and data acquisition are demonstrated.

At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure.

This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects.

The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages:

Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT);Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly;Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model;Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.

"

During the last one and a half decades, wireless sensor networks have witnessed significant growth and tremendous development in both academia and industry. A large number of researchers, including computer scientists and engineers, have been interested in solving challenging problems that span all the layers of the protocol stack of sensor networking systems. Several venues, such as journals, conferences, and workshops, have been launched to cover innovative research and practice in this promising and rapidly advancing field. Because of these trends, I thought it would be beneficial to provide our sensor networks community with a comprehensive reference on as much of the findings as possible on a variety of topics in wireless sensor networks. As this area of research is in continuous progress, it does not seem to be a reasonable solution to keep delaying the publication of such reference any more. This book relates to the second volume and focuses on the advanced topics and applications of wireless sensor networks. Our rationale is that the second volume has all application-specific and non-conventional sensor networks, emerging techniques and advanced topics that are not as matured as what is covered in the first volume. Thus, the second volume deals with three-dimensional, underground, underwater, body-mounted, and societal networks. Following Donald E. Knuth's above-quoted elegant strategy to focus on several important fields (The Art of Computer Programming: Fundamental Algorithms, 1997), all the book chapters in this volume include up-to-date research work spanning various topics, such as stochastic modeling, barrier and spatiotemporal coverage, tracking, estimation, counting, coverage and localization in three-dimensional sensor networks, topology control and routing in three-dimensional sensor networks, underground and underwater sensor networks, multimedia and body sensor networks, and social sensing. Most of these major topics can be covered in an advanced course on wireless sensor networks. This book will be an excellent source of information for graduate students majoring in computer science, computer engineering, electrical engineering, or any related discipline. Furthermore, computer scientists, researchers, and practitioners in both academia and industry will find this book useful and interesting.

RF and Microwave Microelectronics Packaging presents the latest developments in packaging for high-frequency electronics. It will appeal to practicing engineers in the electronic packaging and high-frequency electronics fields and to academic researchers interested in understanding leading issues in the commercial sector. It covers the latest developments in thermal management, electrical/RF/thermal-mechanical designs and simulations, packaging and processing methods as well as other RF/MW packaging-related fields.

This book will explain how to verify SoC logic designs using "formal" and "semi-formal" verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in "functional" verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs.
- First book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs.
- Formal verification of high-level designs (RTL or higher).
- Verification techniques are discussed with associated system-level design methodology.

The ambitious objectives of future road mobility, i.e. fuel efficiency, reduced emissions, and zero accidents, imply a paradigm shift in the concept of the car regarding its architecture, materials, and propulsion technology, and require an intelligent integration into the systems of transportation and power. ICT, components and smart systems have been essential for a multitude of recent innovations, and are expected to be key enabling technologies for the changes ahead, both inside the vehicle and at its interfaces for the exchange of data and power with the outside world. It has been the objective of the International Forum on Advanced Microsystems for Automotive Applications (AMAA) for almost two decades to detect novel trends and to discuss technological implications and innovation potential from day one on. In 2012, the topic of the AMAA conference is "Smart Systems for Safe, Sustainable and Networked Vehicles". The conference papers selected for this book address current research, developments and innovations in the field of ICT, components and systems and other key enabling technologies leading to the automobile and road transport of the future. The book focuses on application fields such as electrification, power train and vehicle efficiency, safety and driver assistance, networked vehicles, as well as components and systems. Additional information is available at www.amaa.de

This book presents a realistic and a holistic review of the microelectronic and semiconductor technology options in the post Moore's Law regime. Technical tradeoffs, from architecture down to manufacturing processes, associated with the 2.5D and 3D integration technologies, as well as the business and product management considerations encountered when faced by disruptive technology options, are presented. Coverage includes a discussion of Integrated Device Manufacturer (IDM) vs Fabless, vs Foundry, and Outsourced Assembly and Test (OSAT) barriers to implementation of disruptive technology options. This book is a must-read for any IC product team that is considering getting off the Moore's Law track, and leveraging some of the More-than-Moore technology options for their next microelectronic product.

Human lives are getting increasingly entangled with technology, especially comp- ing and electronics. At each step we take, especially in a developing world, we are dependent on various gadgets such as cell phones, handheld PDAs, netbooks, me- cal prosthetic devices, and medical measurement devices (e.g., blood pressure m- itors, glucometers). Two important design constraints for such consumer electronics are their form factor and battery life. This translates to the requirements of reduction in the die area and reduced power consumption for the semiconductor chips that go inside these gadgets. Performance is also important, as increasingly sophisticated applications run on these devices, and many of them require fast response time. The form factor of such electronics goods depends not only on the overall area of the chips inside them but also on the packaging, which depends on thermal ch- acteristics. Thermal characteristics in turn depend on peak power signature of the chips. As a result, while the overall energy usage reduction increases battery life, peak power reduction in?uences the form factor. One more important aspect of these electronic equipments is that every 6 months or so, a newer feature needs to be added to keep ahead of the market competition, and hence new designs have to be completed with these new features, better form factor, battery life, and performance every few months. This extreme pressure on the time to market is another force that drives the innovations in design automation of semiconductor chips.

Chalcopyrites, in particular those with a wide band gap, are fascinating materials in terms of their technological potential in the next generation of thin-film solar cells and in terms of their basic material properties. They exhibit uniquely low defect formation energies, leading to unusual doping and phase behavior and to extremely benign grain boundaries. This book collects articles on a number of those basic material properties of wide-gap chalcopyrites, comparing them to their low-gap cousins. They explore the doping of the materials, the electronic structure and the transport through interfaces and grain boundaries, the formation of the electric field in a solar cell, the mechanisms and suppression of recombination, the role of inhomogeneities, and the technological role of wide-gap chalcopyrites.

There is a wide field of tasks left that can only be satisfyingly attacked with the help of old-fashioned analogue technology, and one of the most important are amplifiers for analogue signals. The strongly expanded content of the second edition of "the sound of silence" leads to affordable amplifier design approaches which will end up in lowest-noise solutions not far away from the edge of physical boundaries set by room temperature and given cartridges - thus, fully compatible with very expensive so called "high-end" or "state-of-the-art" offers on today markets - and, from a noise point of view in most cases outperforming them

With easy to follow mathematical treatment it is demonstrated as well that theory is not far away from reality. Measured SNs will be found within 1dB off the calculated ones and deviations from the exact amplifier transfer won't cross the 0.1dB tolerance lines. Additionally, the book presents measurement set-ups and results. Consequently, comparisons with measurement results of test magazine will soon become easier to perform.

This new edition includes a new chapters about reference levels, Noise in Amp Input sections, Humming Problems, and much more."

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification and exhaustive coverage models for functional coverage, thereby drastically reducing their time to design, debug and cover. This updated third edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures. * Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics; * Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage languages and methodologies; * Provides practical applications of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; * Explains each concept in a step-by-step fashion and applies it to a practical real life example; * Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.

This monograph covers some selected problems of positive and fractional electrical circuits composed of resistors, coils, capacitors and voltage (current) sources. The book consists of 8 chapters, 4 appendices and a list of references. Chapter 1 is devoted to fractional standard and positive continuous-time and discrete-time linear systems without and with delays. In chapter 2 the standard and positive fractional electrical circuits are considered and the fractional electrical circuits in transient states are analyzed. Descriptor linear electrical circuits and their properties are investigated in chapter 3, while chapter 4 is devoted to the stability of fractional standard and positive linear electrical circuits. The reachability, observability and reconstructability of fractional positive electrical circuits and their decoupling zeros are analyzed in chapter 5. The fractional linear electrical circuits with feedbacks are considered in chapter 6. In chapter 7 solutions of minimum energy control for standard and fractional systems with and without bounded inputs is presented. In chapter 8 the fractional continuous-time 2D linear systems described by the Roesser type models are investigated.

This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications. A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13um RF CMOS technology for use in highly-linear, low-cost UWB Radio-over-Fiber communication systems."

Design exibility and power consumption in addition to the cost, have always been the most important issues in design of integrated circuits (ICs), and are the main concerns of this research, as well. Energy Consumptions: Power dissipation (P ) and energy consumption are - diss pecially importantwhen there is a limited amountof power budgetor limited source of energy. Very common examples are portable systems where the battery life time depends on system power consumption. Many different techniques have been - veloped to reduce or manage the circuit power consumption in this type of systems. Ultra-low power (ULP) applications are another examples where power dissipation is the primary design issue. In such applications, the power budget is so restricted that very special circuit and system level design techniquesare needed to satisfy the requirements. Circuits employed in applications such as wireless sensor networks (WSN), wearable battery powered systems [1], and implantable circuits for biol- ical applications need to consume very low amount of power such that the entire system can survive for a very long time without the need for changingor recharging battery[2-4]. Using newpowersupplytechniquessuchas energyharvesting[5]and printable batteries [6], is another reason for reducing power dissipation. Devel- ing special design techniques for implementing low power circuits [7-9], as well as dynamic power management (DPM) schemes [10] are the two main approaches to control the system power consumption. Design Flexibility: Design exibility is the other important issue in modern in- grated systems.

This book provides a comprehensive methodology for automated design, test and diagnosis, and use of robust, low-cost, and manufacturable digital microfluidic systems. It focuses on the development of a comprehensive CAD optimization framework for digital microfluidic biochips that unifies different design problems. With the increase in system complexity and integration levels, biochip designers can utilize the design methods described in this book to evaluate different design alternatives, and carry out design-space exploration to obtain the best design point.

This book addresses the theoretical and practical circuit and system concepts that underpin the design of reliable and reproducible, high performance, monolithic feedback circuits. It is intended for practicing electronics engineers and students who wish to acquire an insightful understanding of the ways in which open loop topologies, closed loop architectures, and fundamental circuit theoretic issues combine to determine the limits of performance of analog networks. Since many of the problems that underpin high speed digital circuit design are a subset of the analysis and design dilemmas confronted by wideband analog circuit designers, the book is also germane to high performance digital circuit design.

This textbook presents the mathematical theory and techniques necessary for analyzing and modeling high-performance global networks, such as the Internet. The three main building blocks of high-performance networks are links, switching equipment connecting the links together and software employed at the end nodes and intermediate switches. This book provides the basic techniques for modeling and analyzing these last two components. Topics covered include, but are not limited to: Markov chains and queuing analysis, traffic modeling, interconnection networks and switch architectures and buffering strategies.

This text/reference provides background for those new to the field, gives numerous problems sets and practical examples, and discusses computer aided design and analysis. Annotation copyright Book News, Inc. Portland, Or.