This thesis focuses on the dynamics of autonomous Boolean networks, on the basis of Boolean logic functions in continuous time without external clocking. These networks are realized with integrated circuits on an electronic chip as a field programmable gate array (FPGA) with roughly 100,000 logic gates, offering an extremely flexible model system. It allows fast and cheap design cycles and large networks with arbitrary topologies and coupling delays. The author presents pioneering results on theoretical modeling, experimental realization, and selected applications. In this regard, three classes of novel dynamic behavior are investigated: (i) Chaotic Boolean networks are proposed as high-speed physical random number generators with high bit rates. (ii) Networks of periodic Boolean oscillators are home to long-living transient chimera states, i.e., novel patterns of coexisting domains of spatially coherent (synchronized) and incoherent (desynchronized) dynamics. (iii) Excitable networks exhibit cluster synchronization and can be used as fast artificial Boolean neurons whose spiking patterns can be controlled. This work presents the first experimental platform for large complex networks, which will facilitate exciting future developments.

This book presents a new FPGA architecture known as tree-based FPGA architecture, due to its hierarchical nature. This type of architecture has been relatively unexplored despite their better performance and predictable routing behavior, as compared to mesh-based FPGA architectures. In this book, we explore and optimize the tree-based architecture and we evaluate it by comparing it to equivalent mesh-based FPGA architectures.

This book contains a selection of papers presented at the 17th AISEM ( Associazione Italiana Sensori e Microsistemi ) National Conference on Sensors and Microsystems, held in Brescia, 5-7 February, 2013. The conference highlighted state-of-the-art results from both theoretical and applied research in the field of sensors and related technologies. This book presents material in an interdisciplinary approach, covering many aspects of the disciplines related to sensors, including physics, chemistry, materials science, biology and applications."

This book presents physical understanding, modeling and simulation, on-chip characterization, layout solutions, and design techniques that are effective to enhance the reliability of various circuit units. The authors provide readers with techniques for state of the art and future technologies, ranging from technology modeling, fault detection and analysis, circuit hardening, and reliability management.

This book will introduce new techniques for detecting and diagnosing small-delay defects in integrated circuits. Although this sort of timing defect is commonly found in integrated circuits manufactured with nanometer technology, this will be the first book to introduce effective and scalable methodologies for screening and diagnosing small-delay defects, including important parameters such as process variations, crosstalk, and power supply noise.

This book highlights the complex issues, tasks and skills that must be mastered by an IP designer, in order to design an optimized and robust digital circuit to solve a problem. The techniques and methodologies described can serve as a bridge between specifications that are known to the designer and RTL code that is final outcome, reducing significantly the time it takes to convert initial ideas and concepts into right-first-time silicon. Coverage focuses on real problems rather than theoretical concepts, with an emphasis on design techniques across various aspects of chip-design.

This book describes for researchers in the fields of compiler technology, design and test, and electronic design automation the new area of digital microfluidic biochips (DMBs), and thus offers a new application area for their methods. The authors present a routing-based model of operation execution, along with several associated compilation approaches, which progressively relax the assumption that operations execute inside fixed rectangular modules. Since operations can experience transient faults during the execution of a bioassay, the authors show how to use both offline (design time) and online (runtime) recovery strategies. The book also presents methods for the synthesis of fault-tolerant application-specific DMB architectures. * Presents the current models used for the research on compilation and synthesis techniques of DMBs in a tutorial fashion; * Includes a set of "benchmarks", which are presented in great detail and includes the source code of most of the techniques presented, including solutions to the basic compilation and synthesis problems; * Discusses several new research problems in detail, using numerous examples.

This book presents a case study on a new approach for the optimum design of rooftop, grid-connected photovoltaic-system installation. The study includes two scenarios using different brands of commercially available PV modules and inverters. It investigates and compares several different rooftop grid-connected PV-system configurations taking into account PV modules and inverter specifications. The book also discusses the detailed dynamic MATLAB/Simulink model of the proposed rooftop grid-connected PV system, and uses this model to estimate the energy production capabilities, cost of energy (COE), simple payback time (SPBT) and greenhouse gas (GHG) emissions for each configuration. The book then presents a comprehensive small signal MATLAB/Simulink model for the DC-DC converter operated under continuous conduction mode (CCM). First, the buck converter is modeled using state-space average model and dynamic equations, depicting the converter, are derived. Then a detailed MATLAB/Simulink model utilizing SimElectronics (R) Toolbox is developed. Lastly, the robustness of the converter model is verified against input voltage variations and step load changes.

Overcoming the agility limitations of conventional frequency synthesizers in multi-band OFDM ultra wideband is a key research goal in digital technology. This volume outlines a frequency plan that can generate all the required frequencies from a single fixed frequency, able to implement center frequencies with no more than two levels of SSB mixing. It recognizes the need for future synthesizers to bypass on-chip inductors and operate at low voltages to enable the increased integration and efficiency of networked appliances. The author examines in depth the architecture of the dividers that generate the necessary frequencies from a single base frequency and are capable of establishing a fractional division ratio.

Presenting the first CMOS inductorless single PLL 14-band frequency synthesizer for MB-OFDMUWB makes this volume a key addition to the literature, and with the synthesizer capable of arbitrary band-hopping in less than two nanoseconds, it operates well within the desired range on a 1.2-volt power supply. The author's close analysis of the operation, stability, and phase noise of injection-locked regenerative frequency dividers will provide researchers and technicians with much food for developmental thought.

"

This book describes the integration, characterization and analysis of cost-efficient thin-film transistors (TFTs), applying zinc oxide as active semiconductors. The authors discuss soluble gate dielectrics, ZnO precursors, and dispersions containing nanostructures of the material, while different transistor configurations are analyzed with respect to their integration, compatibility, and device performance. Additionally, simple circuits (inverters and ring oscillators) and a complementary design employing (in)organic semiconducting materials are presented and discussed. Readers will benefit from concise information on cost-efficient materials and processes, applied in flexible and transparent electronic technology, such as the use of solution-based materials and dispersion containing nanostructures, as well as discussion of the physical fundamentals responsible for the operation of the thin-film transistors and the non-idealities of the device.

This book provides an overview of and essential insights on invasive computing. Pursuing a comprehensive approach, it addresses proper concepts, invasive language constructs, and the principles of invasive hardware. The main focus is on the important topic of how to map task-parallel applications to future multi-core architectures including 1,000 or more processor units. A special focus today is the question of how applications can be mapped onto such architectures while not only taking into account functional correctness, but also non-functional execution properties such as execution times and security properties. The book provides extensive experimental evaluations, investigating the benefits of applying invasive computing and hybrid application mapping to give guarantees on non-functional properties such as timing, energy, and security. The techniques in this book are presented in a step-by-step manner, supported by examples and figures. All proposed ideas for providing guarantees on performance, energy consumption, and security are enabled by using the concept of invasive computing and the exclusive usage of resources.

The book summarizes the findings and contributions of the European ARTEMIS project, CESAR, for improving and enabling interoperability of methods, tools, and processes to meet the demands in embedded systems development across four domains - avionics, automotive, automation, and rail. The contributions give insight to an improved engineering and safety process life-cycle for the development of safety critical systems. They present new concept of engineering tools integration platform to improve the development of safety critical embedded systems and illustrate capacity of this framework for end-user instantiation to specific domain needs and processes. They also advance state-of-the-art in component-based development as well as component and system validation and verification, with tool support. And finally they describe industry relevant evaluated processes and methods especially designed for the embedded systems sector as well as easy adoptable common interoperability principles for software tool integration.

This book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM). Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.

Focusing on inductive wireless power transfer (WPT), which relies on coil resonators and power converters, this book begins by providing the background and basic theories of WPT, which are essential for newcomers to the field. Then two major challenges of WPT - power transfer distance and efficiency - are subsequently addressed, and multi-resonator WPT systems, which not only offer a way to extend power transfer distance but also provide more flexibility, are investigated. Recent findings on techniques to maximize the power transfer efficiency of WPT systems, e.g. maximum efficiency point tracking, are also introduced. Without the constraint of cables, wireless power transfer (WPT) is an elegant technique for charging or powering a range of electrical devices, e.g. electric vehicles, mobile phones, artificial hearts, etc. Given its depth of coverage, the book can serve as a technical guideline or reference guide for engineers and researchers working on WPT.

This book presents a comprehensive, systematic approach to the development of vision system architectures that employ sensory-processing concurrency and parallel processing to meet the autonomy challenges posed by a variety of safety and surveillance applications. Coverage includes a thorough analysis of resistive diffusion networks embedded within an image sensor array. This analysis supports a systematic approach to the design of spatial image filters and their implementation as vision chips in CMOS technology. The book also addresses system-level considerations pertaining to the embedding of these vision chips into vision-enabled wireless sensor networks.Describes a system-level approach for designing of vision devices and embedding them into vision-enabled, wireless sensor networks; Surveys state-of-the-art, vision-enabled WSN nodes; Includes details of specifications and challenges of vision-enabled WSNs; Explains architectures for low-energy CMOS vision chips with embedded, programmable spatial filtering capabilities; Includes considerations pertaining to the integration of vision chips into off-the-shelf WSN platforms."

This book is a collection of best selected research papers presented at the 6th International Conference on Opto-Electronics and Applied Optics (OPTRONIX 2020) organized by the University of Engineering & Management, Kolkata, India, in June 2020. The primary focus is to address issues and developments in optoelectronics with particular emphasis on communication technology, IoT and intelligent systems, information processing and its different kinds. The theme of the book is in alignment with the theme of the conference "Advances in Smart Communication Technology and Information Processing." The purpose of this book is to inform the scientists and researchers of this field in India and abroad about the latest developments in the relevant field and to raise awareness among the academic fraternity to get them involved in different activities in the years ahead - an effort to realize knowledge-based society.

Embedded software is ubiquitous today. There are millions of lines of embedded code in smart phones, and even more in systems responsible for automotive control, avionics control, weapons control and space missions. Some of these are safety-critical systems whose correctness, timely response, and reliability are of paramount importance. These requirement pose new challenges to system designers. This necessitates that a proper design science, based on "constructive correctness" be developed. Correct-by-construction design and synthesis of embedded software is done in a way so that post-development verification is minimized, and correct operation of embedded systems is maximized. This book presents the state of the art in the design of safety-critical, embedded software. It introduced readers to three major approaches to specification driven, embedded software synthesis/construction: synchronous programming based approaches, models of computation based approaches, and an approach based on concurrent programming with a co-design focused language. It is an invaluable reference for practitioners and researchers concerned with improving the product development life-cycle.

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.

This textbook covers the fundamental concepts of analog communications with a Q&A approach. It is a comprehensive compilation of numerical problems and solutions covering all the topics in analog communications. Richly illustrated with figures, this book covers the important topics of signals and systems, random variables and random processes, amplitude modulation, frequency modulation, pulse code modulation and noise in analog modulation. It has numerical questions and their solutions clearing the concepts of Fourier transform, Hilbert transform, modulation, synchronization, signal-to-noise ratio analysis and many more. All the solutions have step-by-step approach for easy understanding. This book will be of great interest to the students of electronics and electrical communications engineering.

This book comprises the proceedings of 1st International Conference on Computational Advancement in Communication Circuits and Systems (ICCACCS 2014) organized by Narula Institute of Technology under the patronage of JIS group, affiliated to West Bengal University of Technology. The conference was supported by Technical Education Quality Improvement Program (TEQIP), New Delhi, India and had technical collaboration with IEEE Kolkata Section, along with publication partner by Springer. The book contains 62 refereed papers that aim to highlight new theoretical and experimental findings in the field of Electronics and communication engineering including interdisciplinary fields like Advanced Computing, Pattern Recognition and Analysis, Signal and Image Processing. The proceedings cover the principles, techniques and applications in microwave & devices, communication & networking, signal & image processing, and computations & mathematics & control. The proceedings reflect the conference's emphasis on strong methodological approaches and focus on applications within the domain of Computational Advancement in Communication Circuits and Systems. The content also emphasizes the emerging technologies in the Electronics and Communication field together in close examinations of practices, problems and trends.

The subject of this book is to introduce a model-based quantitative performance indicator methodology applicable for performance, cost and reliability optimization of non-volatile memories. The complex example of flash memories is used to introduce and apply the methodology. It has been developed by the author based on an industrial 2-bit to 4-bit per cell flash development project. For the first time, design and cost aspects of 3D integration of flash memory are treated in this book.

Cell, array, performance and reliability effects of flash memories are introduced and analyzed. Key performance parameters are derived to handle the flash complexity. A performance and array memory model is developed and a set of performance indicators characterizing architecture, cost and durability is defined.

Flash memories are selected to apply the Performance Indicator Methodology to quantify design and technology innovation. A graphical representation based on trend lines is introduced to support a requirement based product development process.

The Performance Indicator methodology is applied to demonstrate the importance of hidden memory parameters for a successful product and system development roadmap.

"Flash Memories "offers an opportunity to enhance your understanding of product development key topics such as:

. Reliability optimization of flash memories is all about threshold voltage margin understanding and definition;
. Product performance parameter are analyzed in-depth in all aspects in relation to the threshold voltage operation window;
. Technical characteristics are translated into quantitative performance indicators;
. Performance indicators are applied to identify and quantify product and technology innovation within adjacent areas to fulfill the application requirements with an overall cost optimized solution; . Cost, density, performance and durability values are combined into a common factor - performance indicator - which fulfills the application requirements"

This book introduces a generic and systematic design-time/run-time methodology for handling the dynamic nature of modern embedded systems, without adding large safety margins in the design. The techniques introduced can be utilized on top of most existing static mapping methodologies to deal effectively with dynamism and to increase drastically their efficiency. This methodology is based on the concept of system scenarios, which group system behaviors that are similar from a multi-dimensional cost perspective, such as resource requirements, delay, and energy consumption. Readers will be enabled to design systems capable to adapt to current inputs, improving system quality and/or reducing cost, possibly learning on-the-fly during execution. Provides an effective solution to deal with dynamic system design Includes a broad survey of the state-of-the-art approaches in this domain Enables readers to design for substantial cost improvements (e.g. energy reductions), by exploiting system scenarios Demonstrates how the methodology has been applied effectively on various, real design problems in the embedded system context

This book provides comprehensive coverage of Network-on-Chip (NoC) security vulnerabilities and state-of-the-art countermeasures, with contributions from System-on-Chip (SoC) designers, academic researchers and hardware security experts. Readers will gain a clear understanding of the existing security solutions for on-chip communication architectures and how they can be utilized effectively to design secure and trustworthy systems.

This book explains the application of recent advances in computational intelligence - algorithms, design methodologies, and synthesis techniques - to the design of integrated circuits and systems. It highlights new biasing and sizing approaches and optimization techniques and their application to the design of high-performance digital, VLSI, radio-frequency, and mixed-signal circuits and systems. This second of two related volumes addresses digital and network designs and applications, with 12 chapters grouped into parts on digital circuit design, network optimization, and applications. It will be of interest to practitioners and researchers in computer science and electronics engineering engaged with the design of electronic circuits.

This thesis explores a route to induce and control the structure formation process in thin films by the use of strong electric fields. We investigate, establish and apply the use of the electrohydrodynamic (EHD) lithography as a versatile patterning tool on the sub-micrometre and nanometre length scales for functional materials. Thin films are ubiquitous, they are found in nature and used in almost every aspect of daily life. While film instabilities are often undesirable in nature and technology, they can be utilized to produce structures by precisely controlling the destabilization of the film. EHD lithography utilizes instabilities induced by means of an electric field to fabricate periodic structures. EHD patterning is set to become a competitive candidate for low-cost lithographic technology for a number of applications. Herein, the applied potential of this lithographic process is explored by expanding its applicability to a broad range of materials and by a simultaneous patterning of multilayer systems or functional polymers yielding hierarchical architectures with novel functionalities.
EHD pattern formation enables for instance, the fabrication of multi-scale structured arrays as surface enhanced Raman scattering (SERS)-active platforms. Furthermore, crystalline and conductive polymers are patterned using the EHD approach and the underlying structure formation mechanisms are discussed. This extension towards functional material systems offers interesting prospects for potential applications. Findings of this thesis are very promising for use in optoelectronic devices.