This book provides comprehensive coverage of the latest trends/advances in subjective and objective quality evaluation for traditional visual signals, such as 2D images and video, as well as the most recent challenges for the field of multimedia quality assessment and processing, such as mobile video and social media. Readers will learn how to ensure the highest storage/delivery/ transmission quality of visual content (including image, video, graphics, animation, etc.) from the server to the consumer, under resource constraints, such as computation, bandwidth, storage space, battery life, etc.

This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets.

The Information and communication technology (ICT) industry is said to account for 2% of the worldwide carbon emissions - a fraction that continues to grow with the relentless push for more and more sophisticated computing equipment, c- munications infrastructure, and mobile devices. While computers evolved in the directionofhigherandhigherperformanceformostofthelatterhalfofthe20thc- tury, the late 1990's and early 2000'ssaw a new emergingfundamentalconcern that has begun to shape our day-to-day thinking in system design - power dissipation. As we elaborate in Chapter 1, a variety of factors colluded to raise power-ef?ciency as a ?rst class design concern in the designer's mind, with profound consequences all over the ?eld: semiconductor process design, circuit design, design automation tools, system and application software, all the way to large data centers. Power-ef?cient System Design originated from a desire to capture and highlight the exciting developments in the rapidly evolving ?eld of power and energy op- mization in electronic and computer based systems. Tremendous progress has been made in the last two decades, and the topic continues to be a fascinating research area. To develop a clearer focus, we have concentrated on the relatively higher level of design abstraction that is loosely called the system level. In addition to the ext- sive coverage of traditional power reduction targets such as CPU and memory, the book is distinguished by detailed coverage of relatively modern power optimization ideas focussing on components such as compilers, operating systems, servers, data centers, and graphics processors.

More and more information, audio and video but also a range of other information type, is generated, processed and used by machines today, even though the end user may be a human. The result over the past 15 years has been a substantial increase in the type of information and change in the way humans generate, classify, store, search, access and consume information. Conversion of information to digital form is a prerequisite for this enhanced machine role, but must be done having in mind requirements such as compactness, fidelity, interpretability etc. This book presents new ways of dealing with digital information and new types of digital information underpinning the evolution of society and business.

The aim of this book is to expand and improve upon the existing knowledge on discrete-time 1-bit look-ahead sigma-delta modulation in general, and to come to a solution for the above mentioned specific issues arising from 1-bit sigma-delta modulation for SA-CD. In order to achieve this objective an analysis is made of the possibilities for improving the performance of digital noise-shaping look-ahead solutions. On the basis of the insights obtained from the analysis, several novel generic 1-bit look-ahead solutions that improve upon the state-of-the-art will be derived and their performance will be evaluated and compared. Finally, all the insights are combined with the knowledge of the SA-CD lossless data compression algorithm to come to a specifically for SA-CD optimized look-ahead design.

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification and exhaustive coverage models for functional coverage, thereby drastically reducing their time to design, debug and cover. This updated third edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures. * Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics; * Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage languages and methodologies; * Provides practical applications of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; * Explains each concept in a step-by-step fashion and applies it to a practical real life example; * Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.

Modeling of photovoltaic sources and their emulation by means of power electronic converters are challenging issues. The former is tied to the knowledge of the electrical behavior of the PV generator; the latter consists in its realization by a suitable power amplifier. This extensive introduction to the modeling of PV generators and their emulation by means of power electronic converters will aid in understanding and improving design and set up of new PV plants. The main benefit of reading Photovoltaic Sources is the ability to face the emulation of photovoltaic generators obtained by the design of a suitable equipment in which voltage and current are the same as in a real source. This is achieved according to the following steps: the source electrical behavior modeling, the power converter design, including its control, for the laboratory emulator. This approach allows the reader to cope with the creation of an indoor virtual photovoltaic plant, in which the environmental conditions can be imposed by the user, for testing real operation including maximum power point tracking, partial shading, control for the grid or load interfacing, etc. Photovoltaic Sources is intended to meet the demands of postgraduate level students, and should prove useful to professional engineers and researchers dealing with the problems associated with modeling and emulation of photovoltaic sources.

This book is about security in embedded systems and it provides an authoritative reference to all aspects of security in system-on-chip (SoC) designs. The authors discuss issues ranging from security requirements in SoC designs, definition of architectures and design choices to enforce and validate security policies, and trade-offs and conflicts involving security, functionality, and debug requirements. Coverage also includes case studies from the "trenches" of current industrial practice in design, implementation, and validation of security-critical embedded systems. Provides an authoritative reference and summary of the current state-of-the-art in security for embedded systems, hardware IPs and SoC designs; Takes a "cross-cutting" view of security that interacts with different design and validation components such as architecture, implementation, verification, and debug, each enforcing unique trade-offs; Includes high-level overview, detailed analysis on implementation, and relevant case studies on design/verification/debug issues related to IP/SoC security.

Tin (Sn) whiskers are electrically conductive, single crystal eruptions that grow from Sn film surfaces. Their high aspect ratio presents reliability problems for the electronics industry due to bridging and metal arcing, leading to malfunctions and catastrophic failures in many electronic systems (including satellite and defense sectors). Due to legislation in the EU, Japan, and the U.S., mandating a gradual shift from lead (Pb)-based to lead-free solders and board finishes, there has been a reemergence of Sn whiskers. Continuing reports of Sn whisker induced failures coupled with the lack of an industry-accepted understanding of whisker growth and/or test methods to identify whisker prone products has made pure/high Sn substitutes a risky proposition in high reliability systems. This thesis is designed to clarify and control the fundamental mechanisms that govern whisker formation. The research focuses on reproducible "laboratory" created whiskers under a variety of rigorously controlled environmental factors such as film thickness, film stress, substrate material, gas environment, and humidity exposure, which are known to play a significant role in whisker production. The ultimate question of how to impede and/or prevent whisker growth is also addressed and shows that whisker prevention is possible via hard metal capping films, which are impenetrable by whiskers.

Today s semiconductor memory market is divided between two types of memory: DRAM and Flash. Each has its own advantages and disadvantages. While DRAM is fast but volatile, Flash is non-volatile but slow. A memory system based on self-organized quantum dots (QDs) as storage node could combine the advantages of modern DRAM and Flash, thus merging the latter s non-volatility with very fast write times.

This thesis investigates the electronic properties of and carrier dynamics in self-organized quantum dots by means of time-resolved capacitance spectroscopy and time-resolved current measurements. The first aim is to study the localization energy of various QD systems in order to assess the potential of increasing the storage time in QDs to non-volatility. Surprisingly, it is found that the major impact of carrier capture cross-sections of QDs is to influence, and at times counterbalance, carrier storage in addition to the localization energy. The second aim is to study the coupling between a layer of self-organized QDs and a two-dimensional hole gas (2DHG), which is relevant for the read-out process in memory systems. The investigation yields the discovery of the many-particle ground states in the QD ensemble.In addition to its technological relevance, the thesis also offers new insights into the fascinating field of nanostructure physics."

As diverse as tomorrow's society constituent groups may be, they will share the common requirements that their life should become safer and healthier, offering higher levels of effectiveness, communication and personal freedom. The key common part to all potential solutions fulfilling these requirements is wearable embedded systems, with longer periods of autonomy, offering wider functionality, more communication possibilities and increased computational power. As electronic and information systems on the human body, their role is to collect relevant physiological information, and to interface between humans and local and/or global information systems. Within this context, there is an increasing need for applications in diverse fields, from health to rescue to sport and even remote activities in space, to have real-time access to vital signs and other behavioral parameters for personalized healthcare, rescue operation planning, etc. This book's coverage will span all scientific and technological areas that define wearable monitoring systems, including sensors, signal processing, energy, system integration, communications, and user interfaces. Six case studies will be used to illustrate the principles and practices introduced.

Wafer-scale integration has long been the dream of system designers. Instead of chopping a wafer into a few hundred or a few thousand chips, one would just connect the circuits on the entire wafer. What an enormous capability wafer-scale integration would offer: all those millions of circuits connected by high-speed on-chip wires. Unfortunately, the best known optical systems can provide suitably ?ne resolution only over an area much smaller than a whole wafer. There is no known way to pattern a whole wafer with transistors and wires small enough for modern circuits. Statistical defects present a ?rmer barrier to wafer-scale integration. Flaws appear regularly in integrated circuits; the larger the circuit area, the more probable there is a ?aw. If such ?aws were the result only of dust one might reduce their numbers, but ?aws are also the inevitable result of small scale. Each feature on a modern integrated circuit is carved out by only a small number of photons in the lithographic process. Each transistor gets its electrical properties from only a small number of impurity atoms in its tiny area. Inevitably, the quantized nature of light and the atomic nature of matter produce statistical variations in both the number of photons de?ning each tiny shape and the number of atoms providing the electrical behavior of tiny transistors. No known way exists to eliminate such statistical variation, nor may any be possible.

Given the widespread use of real-time multitasking systems, there are tremendous optimization opportunities if reconfigurable computing can be effectively incorporated while maintaining performance and other design constraints of typical applications. The focus of this book is to describe the dynamic reconfiguration techniques that can be safely used in real-time systems. This book provides comprehensive approaches by considering synergistic effects of computation, communication as well as storage together to significantly improve overall performance, power, energy and temperature."

This unique book provides an up-to-date overview of the concepts behind lead-free soldering techniques. Readers will find a description of the physical and mechanical properties of lead-free solders, in addition to lead-free electronics and solder alloys. Additional topics covered include the reliability of lead-free soldering, tin whiskering and electromigration, in addition to emerging technologies and research.

The goal of Ultra-Low Voltage Nano-Scale Memories is to provide a detailed explanation of the state-of-the-art nanometer and sub-1-V memory LSIs that are playing decisive roles in power conscious systems. Emerging problems between the device, circuit, and system levels are systematically discussed in terms of reliable high-speed operations of memory cells and peripheral logic circuits. The effectiveness of solutions at device and circuit levels is also described at length. Voltage scaling is prevented by many resulting problems, such as the ever-decreasing signal-to-noise-ratio and voltage margin of many tiny flip-flop circuits in a memory-cell array and peripheral circuits, and the ever-increasing leakage and variation in speed caused by variations in process, voltage, and temperature. The problems and promising solutions at device and circuit levels are discussed in detail through clarifying noise components in an array, and even essential differences in ultra-low voltage operations between DRAMs and SRAMs. Moreover, various kinds of on-chip voltage converters necessary to solve the problems with internal power-supply managements are widely and deeply discussed. experience in memory and low-voltage designs in industry, bridging the different necessary technologies between memory, digital, and analog technologies, and even between DRAMs and SRAMs. A lot of knowledge that authors have acquired to date, and circuits that authors regard as important are covered from the basics to the state-of-the-art. Thus, the book is beneficial to students and engineers interested in ultra-low voltage nano-scale LSIs. Moreover, it is instructive not only for memory designers, but also for all digital and analog LSI designers who are the front edge of such LSI developments, since it is full of insight to develop such LSIs.

Noise is a fundamental problem that degrades the performance of every communications device. Noise starts at a very basic level - in the circuits within communications devices and systems. This book is a comprehensive treatment of how noise affects circuit performance. It covers practical methods for optimizing communications performance in a noisy environment. Special coverage is given to phase noise in oscillator circuits, which is a critical problem in cellular and mobile telecommunications. Software has become an indispensable tool for analyzing noise. This book gives circuit designers and software developers a solid understanding of this specialized software, so they can more effectively create noise-resistant circuitry. Noise is the basic stumbling block in creating reliable communications circuits, and this book shows engineers how to overcome this problem.

An effective and cost efficient protection of electronic system against ESD stress pulses specified by IEC 61000-4-2 is paramount for any system design. This pioneering book presents the collective knowledge of system designers and system testing experts and state-of-the-art techniques for achieving efficient system-level ESD protection, with minimum impact on the system performance. All categories of system failures ranging from 'hard' to 'soft' types are considered to review simulation and tool applications that can be used. The principal focus of System Level ESD Co-Design is defining and establishing the importance of co-design efforts from both IC supplier and system builder perspectives. ESD designers often face challenges in meeting customers' system-level ESD requirements and, therefore, a clear understanding of the techniques presented here will facilitate effective simulation approaches leading to better solutions without compromising system performance. With contributions from Robert Ashton, Jeffrey Dunnihoo, Micheal Hopkins, Pratik Maheshwari, David Pomerenke, Wolfgang Reinprecht, and Matti Usumaki, readers benefit from hands-on experience and in-depth knowledge in topics ranging from ESD design and the physics of system ESD phenomena to tools and techniques to address soft failures and strategies to design ESD-robust systems that include mobile and automotive applications. The first dedicated resource to system-level ESD co-design, this is an essential reference for industry ESD designers, system builders, IC suppliers and customers and also Original Equipment Manufacturers (OEMs). Key features: * Clarifies the concept of system level ESD protection. * Introduces a co-design approach for ESD robust systems. * Details soft and hard ESD fail mechanisms. * Detailed protection strategies for both mobile and automotive applications. * Explains simulation tools and methodology for system level ESD co-design and overviews available test methods and standards. * Highlights economic benefits of system ESD co-design.

This book is a single-source guide to nonlinearity and nonlinear techniques in energy harvesting, with a focus on vibration energy harvesters for micro and nanoscale applications. The authors demonstrate that whereas nonlinearity was avoided as an undesirable phenomenon in early energy harvesters, now it can be used as an essential part of these systems. Readers will benefit from an overview of nonlinear techniques and applications, as well as deeper insight into methods of analysis and modeling of energy harvesters, employing different nonlinearities. The role of nonlinearity due to different aspects of an energy harvester is discussed, including nonlinearity due to mechanical-to-electrical conversion, nonlinearity due to conditioning electronic circuits, nonlinearity due to novel materials (e.g., graphene), etc. Coverage includes tutorial introductions to MEMS and NEMS technology, as well as a wide range of applications, such as nonlinear oscillators and transducers for energy harvesters and electronic conditioning circuits for effective energy processing.

Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design.
This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures.
KEY FEATURES
* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends
* Detailed analysis of all popular standards for on-chip communication architectures
* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts
* Future trends that with have a significant impact on research and design of communication architectures over the next several years

With vastly increased complexity and functionality in the "nanometer era" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. This is due primarily to the inevitable increase in the distance among circuit elements and interconnect design solutions have become the greatest determining factor in overall performance.
Three-dimensional (3D) integrated circuits (ICs), which contain multiple layers of active devices, have the potential to enhance dramatically chip performance and functionality, while reducing the distance among devices on a chip. They promise solutions to the current "interconnect bottleneck" challenges faced by IC designers. They also may facilitate the integration of heterogeneous materials, devices, and signals. However, before these advantages can be realized, key technology challenges of 3D ICs must be addressed.
This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of three-dimensional integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of three-dimensional integrated circuits.
* Demonstrates how to overcome "Interconnect Bottleneck" with 3D Integrated Circuit Design...leading edge design techniques offer solutions to problems (performance/power consumption/price) faced by all circuit designers.
* The FIRST book on 3D Integrated Circuit Design...provides up-to-date information that is otherwise difficult tofind;
* Focuses on design issues key to the product development cyle...good design plays a major role in exploiting the implementation flexibilities offered in the third dimension;
* Provides broad coverage of 3D IC Design, including Interconnect Prediction Models, Thermal Management Techniques, and Timing Optimization...offers practical view of designing 3D circuits.

Modern multimedia systems are becoming increasingly multiprocessor and heterogeneous to match the high performance and low power demands placed on them by the large number of applications. The concurrent execution of these applications causes interference and unpredictability in the performance of these systems. In Multimedia Multiprocessor Systems, an analysis mechanism is presented to accurately predict the performance of multiple applications executing concurrently. With high consumer demand the time-to-market has become significantly lower. To cope with the complexity in designing such systems, an automated design-flow is needed that can generate systems from a high-level architectural description such that they are not error-prone and consume less time. Such a design methodology is presented for multiple use-cases -- combinations of active applications. A resource manager is also presented to manage the various resources in the system, and to achieve the goals of performance prediction, admission control and budget enforcement.

This book describes an alternative method of realizing accurate on-chip frequency references in standard CMOS processes. This method exploits the thermal-diffusivity of silicon, i.e. the rate at which heat diffuses through a silicon substrate. This is the first book describing the design of such electrothermal frequency references. It includes the necessary theory, supported by practical realizations that achieve inaccuracies as low as 0.1% and thus demonstrate the feasibility of this approach. The book also includes several circuit and system-level solutions to the precision circuit design challenges encountered during the design of such frequency references.

Dynamically Reconfigurable Systems is the first ever to focus on the emerging field of Dynamically Reconfigurable Computing Systems. While programmable logic and design-time configurability are well elaborated and covered by various texts, this book presents a unique overview over the state of the art and recent results for dynamic and run-time reconfigurable computing systems.

Reconfigurable hardware is not only of utmost importance for large manufacturers and vendors of microelectronic devices and systems, but also a very attractive technology for smaller and medium-sized companies. Hence, Dynamically Reconfigurable Systems also addresses researchers and engineers actively working in the field and provides them with information on the newest developments and trends in dynamic and run-time reconfigurable systems.

One of the leading causes of automobile accidents is the slow reaction of the driver while responding to a hazardous situation. State-of-the-art wireless electronics can automate several driving functions, leading to significant reduction in human error and improvement in vehicle safety. With continuous transistor scaling, silicon fabrication technology now has the potential to substantially reduce the cost of automotive radar sensors. This book bridges an existing gap between information available on dependable system/architecture design and circuit design. It provides the background of the field and detailed description of recent research and development of silicon-based radar sensors. System-level requirements and circuit topologies for radar transceivers are described in detail. Holistic approaches towards designing radar sensors are validated with several examples of highly-integrated radar ICs in silicon technologies. Circuit techniques to design millimeter-wave circuits in silicon technologies are discussed in depth.