This book introduces a novel design methodology which can significantly reduce the ASIP development effort through high degrees of design automation. The key elements of this new design methodology are a powerful application profiler and an automated instruction-set customization tool which considerably lighten the burden of mapping a target application to an ASIP architecture in the initial design stages. The book includes several design case studies with real life embedded applications to demonstrate how the methodology and the tools can be used in practice for accelerating the overall ASIP design process.

"Long Wave Polar Modes in Semiconductor Heterostructures" is concerned with the study of polar optical modes in semiconductor heterostructures from a phenomenological approach and aims to simplify the model of lattice dynamics calculations. The book provides useful tools for performing calculations relevant to anyone who might be interested in practical applications.

The main focus of "Long Wave Polar Modes in Semiconductor Heterostructures" is planar heterostructures (quantum wells or barriers, superlattices, double barrier structures etc) but there is also discussion on the growing field of quantum wires and dots. Also to allow anyone reading the book to apply the techniques discussed for planar heterostructures, the scope has been widened to include cylindrical and spherical geometries.

The book is intended as an introductory text which guides the reader through basic questions and expands to cover state-of-the-art professional topics. The book is relevant to experimentalists wanting an instructive presentation of a simple phenomenological model and theoretical tools to work with and also to young theoreticians by providing discussion of basic issues and the basis of advanced theoretical formulations. The book also provides a brief respite on the physics of piezoelectric waves as a coupling to polar optical modes.

The electronic circuit is a proud child of twentieth century natural science. In a hundred short years it has developed to the point that it now enhances nearly every aspect of human life. Yet our basic understanding of electronic-circuit operation, electronic -circuittheory, has not made significant progress during the semiconductor industry's explosive growth from 1950s to the present. This is because the electronic circuit has never been considered to be a challenging research subject by physi cists. Linear passive circuit theory was established by the late 1940s. After the advent of the semiconductor electron devices, the interest of the technical community shifted away from circuit theory. Twenty years later, when integrated circuit technology began an explosive growth, cir cuit theory was again left behind in the shadow of rapidly progressing computer-aided design (CAD) technology. The present majority view is that electronic-circuit theory stands in a subordinate position to CAD and to device-processing technology. In 1950s and 1960s, several new semiconductor devices were invented every year, and each new device seemed to have some interesting funda mental physical mechanisms that appeared worth investigating. Com pared to attractive device physics, the problems of the semiconductor device circuit appeared less sophisticated and less attractive. Bright minds of the time drifted away from circuit theory to electron-device physics. After thirty years only one type of semiconductor device, the electron triode with several variations survived, whereas hundreds of them went into oblivion."

This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit's performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.

The book reports modeling and simulation techniques for substrate noise coupling effects in RFICs and introduces isolation structures and design guides to mitigate such effects with the ultimate goal of enhancing the yield of RF and mixed signal SoCs. The book further reports silicon measurements, and new test and noise isolation structures. To the authors knowledge, this is the first title devoted to the topic of substrate noise coupling in RFICs as part of a large SoC.

The second edition of this introductory book sets out clearly and concisely the principles of operation of the semiconductor devices that lie at the heart of the microelectronic revolution.

The book aims to teach the reader how semiconductor devices are modelled. It begins by providing a firm background in the relevant semiconductor physics. These ideas are then used to construct both circuit models and mathematical models for diodes, bipolar transistors and MOSFETs. It also describes the processes involved in fabricating silicon chips containing these devices.

The first edition has already proved a highly useful textbook to first and second year degree students in electrical and electronic engineering, and related disciplines. It is also useful to HND students in similar subject areas, and as supplementary reading for anyone involved in integrated circuit design and fabrication.

The book deals with the numerical simulation of noise in semiconductor devices operating in linear (small-signal) and nonlinear (large-signal) conditions. The main topics of the book are: An overview of the physical basis of noise in semiconductor devices, a detailed treatment of numerical noise simulation in small-signal conditions, and a presentation of innovative developments in the noise simulation of semiconductor devices operating in large-signal quasi-periodic conditions. The main benefit that the reader will derive from the book is the ability to understand, and, if needed, replicate the development of numerical, physics-based noise simulation of semiconductor devices in small-signal and large-signal conditions.

This book introduces systematic design methods for passive and active RF circuits and techniques, including state-of-the-art digital enhancement techniques. As the very first book dedicated to multiband RF circuits and techniques, this work provides an overview of the evolution of transmitter architecture and discusses current digital predistortion techniques. Readers will find a collection of novel research ideas and new architectures in concurrent multiband power dividers, power amplifiers and related digital enhancement techniques. This book will be of great interest to academic researchers, R&D engineers, wireless transmitter and protocol designers, as well as graduate students who wish to learn the core architectures, principles and methods of multiband RF circuits and techniques.

Current-mode design is of great interest to high-tech analog designers today, who are principally concerned with designing whole systems on a chip. This work focuses on the theory and methods of many important current-mode circuit design techniques making it a comprehensive technical overview that fills a gap in the current literature.
The purpose of the book is to compile all available information in the area of OTA-C filters, current conveyor and CFOA based filters, switched-current filters, and log-domain filters into one complete reference volume. Practical applications of current-mode design techniques for realizing practical VLSI systems such as disk drive read channel ICs and video filters are covered in detail. The background required for this book is an exposure to a first course in active RC filters, digital signal processing and optionally, some knowledge of switched capacitor filters.

Innovative Algorithms and Techniques in Automation, Industrial Electronics and Telecommunications includes a set of rigorously reviewed world-class manuscripts addressing and detailing state-of-the-art research projects in the areas of Industrial Electronics, Technology & Automation, Telecommunications and Networking.

Innovative Algorithms and Techniques in Automation, Industrial Electronics and Telecommunications includes selected papers form the conference proceedings of the International Conference on Industrial Electronics, Technology & Automation (IETA 2006) and International Conference on Telecommunications and Networking (TeNe 06) which were part of the International Joint Conferences on Computer, Information and Systems Sciences and Engineering (CISSE 2006).

All aspects of the conference were managed on-line; not only the reviewing, submissions and registration processes; but also the actual conference. Conference participants - authors, presenters and attendees - only needed an internet connection and sound available on their computers in order to be able to contribute and participate in this international ground-breaking conference. The on-line structure of this high-quality event allowed academic professionals and industry participants to contribute work and attend world-class technical presentations based on rigorously refereed submissions, live, without the need for investing significant travel funds or time out of the office. Suffice to say that CISSE received submissions from more than 70 countries, for whose researchers, this opportunity presented a much more affordable, dynamic and well-planned event to attend and submit their work to, versus a classic, on-the-ground conference.

The CISSE conference audio room provided superb audio even over low speed internet connections, the ability to display PowerPoint presentations, and cross-platform compatibility (the conferencing software runs on Windows, Mac, and any other operating system that supports Java). In addition, the conferencing system allowed for an unlimited number of participants, which in turn granted CISSE the opportunity to allow all participants to attend all presentations, as opposed to limiting the number of available seats for each session.

This book focuses on the design of a Mega-Gray (a standard unit of total ionizing radiation) radiation-tolerant ps-resolution time-to-digital converter (TDC) for a light detection and ranging (LIDAR) system used in a gamma-radiation environment. Several radiation-hardened-by-design (RHBD) techniques are demonstrated throughout the design of the TDC and other circuit techniques to improve the TDC's resolution in a harsh environment are also investigated. Readers can learn from scratch how to design a radiation-tolerant IC. Information regarding radiation effects, radiation-hardened design techniques and measurements are organized in such a way that readers can easily gain a thorough understanding of the topic. Readers will also learn the design theory behind the newly proposed delta-sigma TDC. Readers can quickly acquire knowledge about the design of radiation-hardened bandgap voltage references and low-jitter relaxation oscillators, which are introduced in the content from a designer's perspective. * Discusses important aspects of radiation-tolerant analog IC design, including realistic applications and radiation effects on ICs; * Demonstrates radiation-hardened-by-design techniques through a design-test-radiation assessment practice; * Describes a new type of Time-to-Digital (TDC) converter designed for radiation-tolerant application; * Explains the design and measurement of all functional blocks (e.g., bandgap reference, relaxation oscillator) in the TDC.

This book, written by experts in the field, is based on the latest research on the analysis and synthesis of switched time-delay systems. It covers the stability, filtering, fault detection and control problems, which are studied using the average dwell time approach. It presents both the continuous-time and discrete-time systems and provides useful insights and methods, as well as practical algorithms that can be considered in other complex systems, such as neuron networks and genetic regulatory networks, making it a valuable resource for researchers, scientists and engineers in the field of system sciences and control communities.

This book describes how engineers can make optimum use of the two industry standard analysis/design tools, SystemC and SystemC-AMS. The authors use a system-level design approach, emphasizing how SystemC and SystemC-AMS features can be exploited most effectively to analyze/understand a given electronic system and explore the design space. The approach taken by this book enables system engineers to concentrate on only those SystemC/SystemC-AMS features that apply to their particular problem, leading to more efficient design. The presentation includes numerous, realistic and complete examples, which are graded in levels of difficulty to illustrate how a variety of systems can be analyzed with these tools.

. . . ????????????????????????????????? ????????????? ????????????,????? ???? ??????????? ???????????????????? ???. THUCYDIDIS HISTORIAE IV:108 C. Hude ed. , Teubner, Lipsiae MCMXIII ???????????,????? ??,? ????????????????? ???????????????????? ?????? ?????? ?????? ??? ????????? ??? ?' ?????????? ??' ?????????? ? ??????? ??? ????????????? ???????. ???????????????????:108 ???????????? ?????????????????????? ?. ?????????????. ????????????,????? It being the fashion of men, what they wish to be true to admit even upon an ungrounded hope, and what they wish not, with a magistral kind of arguing to reject. Thucydides (the Peloponnesian War Part I), IV:108 Thomas Hobbes Trans. , Sir W. Molesworth ed. In The English Works of Thomas Hobbes of Malmesbury, Vol. VIII I have been introduced to clock design very early in my professional career when I was tapped right out of school to design and implement the clock generation and distribution of the Alpha 21364 microprocessor. Traditionally, Alpha processors - hibited highly innovative clocking systems, always worthy of ISSCC/JSSC publi- tions and for a while Alpha processors were leading the industry in terms of clock performance. I had huge shoes to ?ll. Obviously, I was overwhelmed, confused and highly con?dent that I would drag the entire project down.

Short turnaround has become critical in the design of electronic systems. Software- programmable components such as microprocessors and digital signal processors have been used extensively in such systems since they allow rapid design revisions. However, the inherent performance limitations of software-programmable systems mean that they are inadequate for high-performance designs. Designers thus turned to gate arrays as a solution. User-programmable gate arrays (field-programmable gate arrays, FPGAs) have recently emerged and are changing the way electronic systems are designed and implemented. The growing complexity of the logic circuits that can be packed onto an FPGA chip means that it has become important to have automatic synthesis tools that implement logic functions on these architectures. Logic Synthesis for Field-Programmable Gate Arrays describes logic synthesis for both look-up table (LUT) and multiplexor-based architectures, with a balanced presentation of existing techniques together with algorithms and the system developed by the authors. Audience: A useful reference for VLSI designers, developers of computer-aided design tools, and anyone involved in or with FPGAs.

The author presents current work in bond graph methodology by providing a compilation of contributions from experts across the world that covers theoretical topics, applications in various areas as well as software for bond graph modeling.
It addresses readers in academia and in industry concerned with the analysis of multidisciplinary engineering systems or control system design who are interested to see how latest developments in bond graph methodology with regard to theory and applications can serve their needs in their engineering fields.
This presentation of advanced work in bond graph modeling presents the leading edge of research in this field. It is hoped that it stimulates new ideas with regard to further progress in theory and in applications.

With the proliferation of packaging technology, failure and reliability have become serious concerns. This invaluable reference details processes that enable detection, analysis and prevention of failures. It provides a comprehensive account of the failures of device packages, discrete component connectors, PCB carriers and PCB assemblies.

This book contains more than the IEEE Standard 1149.4. It also contains the thoughts of those who developed the standard. Adam Osseiran has edited the original writings of Brian Wilkins, Colin Maunder, Rod Tulloss, Steve Sunter, Mani Soma, Keith Lofstrom and John McDermid, all of whom have personally contributed to this standard. To preserve the original spirit, only minor changes were made, and the reader will sense a chapter-to-chapter variation in the style of expression. This may appear awkward to some, although I found the Iack of monotonicity refreshing. A system consists of a specific organization of parts. The function of the system cannot be performed by an individual part or even a disorganized collection ofthe same parts. Testing has a system-like characteristic. Testing of a system does not follow directly from the testing of its parts, and a system built with testable parts can sometimes be impossible to test. Therefore, testability of the system must be organized. Some years ago, the IEEE published the boundary-scan Standard 1149.1. That Standard provided an architecture for digital VLSI chips. The chips designed with the 1149.1 architecture can be integrated into a testable system. However, many systems today contain both analog and digital chips. Even if all digital chips are compliant with the standard, the testability of a mixed-signal system cannot be guaranteed. The new Standard 1149.4, described in this book, extends the previous architecture to mixed-signal systems.

High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.

This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video.

Analog circuit design is often the bottleneck when designing mixed analog-digital systems. A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits presents a new methodology based on a top-down, constraint-driven design paradigm that provides a solution to this problem. This methodology has two principal advantages: (1) it provides a high probability for the first silicon which meets all specifications, and (2) it shortens the design cycle. A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits is part of an ongoing research effort at the University of California at Berkeley in the Electrical Engineering and Computer Sciences Department. Many faculty and students, past and present, are working on this design methodology and its supporting tools. The principal goals are: (1) developing the design methodology, (2) developing and applying new tools, and (3) proving' the methodology by undertaking industrial strength' design examples. The work presented here is neither a beginning nor an end in the development of a complete top-down, constraint-driven design methodology, but rather a step in its development. This work is divided into three parts. Chapter 2 presents the design methodology along with foundation material. Chapters 3-8 describe supporting concepts for the methodology, from behavioral simulation and modeling to circuit module generators. Finally, Chapters 9-11 illustrate the methodology in detail by presenting the entire design cycle through three large-scale examples. These include the design of a current source D/A converter, a Sigma-Delta A/D converter, and a video driver system. Chapter 12 presents conclusions and current research topics. A Top-Down, Constraint-Driven Design Methodology for Analog Integrated Circuits will be of interest to analog and mixed-signal designers as well as CAD tool developers.

In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. The basic concept and classical ATPG algorithms are reviewed. Then, the formulation as a SAT problem is considered. As the underlying engine, modern SAT solvers and their use on circuit related problems are comprehensively discussed. Advanced techniques for SAT-based ATPG are introduced and evaluated in the context of an industrial environment. The chapters of the book cover efficient instance generation, encoding of multiple-valued logic, usage of various fault models, and detailed experiments on multi-million gate designs. The book describes the state of the art in the field, highlights research aspects, and shows directions for future work.

Analog design still has, unfortunately, a flavor of art. Art can be beautiful. However, art in itself is difficult to teach to students and difficult to transfer from experienced analog designers to new trainee designers in companies. Structured Electronic Design: High-Performance Harmonic Oscillators and Bandgap References aims to systemize analog design. The use of orthogonalization of the design of the fundamental quality aspects (noise, distortion, and bandwidth) and hierarchy in the subsequent design steps, enables designers to achieve high-performance designs, in a relatively short time. As a result of the systematic design procedure, the effect of design decisions on the circuit performance is made clear. Additionally, the use of resources for reaching a specified performance is tracked. This book, therefore, describes the structured electronic design of high-performance harmonic oscillators and bandgap references. The structured design of harmonic oscillators includes the maximization of the carrier-to- noise ratio by means of tapping, i.e. an impedance adaption method for noise matching. The bandgap reference, a popular implementation of a voltage reference, is studied via the unusual concept of the linear combination of base-emitter voltages. The presented method leads to the design of high-performance references in CMOS and Bipolar technology. Using this concept, on a high level of abstraction the quality with respect to, for instance, noise and power-supply rejection can be identified. In this book, it is shown with several design examples that this method provides an excellent starting point for the design of high-performance bandgap references. Auxiliary to the harmonic-oscillator and bandgap reference design are the negative- feedback amplifiers. In this book the systematic design of the dynamic behavior is emphasized. By means of the identification of the dominant poles, it is possible to give an upper limit of the attainable bandwidth, even before the real frequency compensation is accomplished. Structured Electronic Design: High-Performance Harmonic Oscillators and Bandgap References is a valuable book for researchers and designers, as well as students in the field of analog design. It helps both the experienced and trainee designer to come to grips with the design of analog circuits. The presented method is illustrated by several well- described design examples.

Advances in the state of the art mean the signal processing ICs of ever-increasing complexity are being introduced. While the typical portion of a large IC devoted to analog circuits has diminished, the performance of those surviving analog signal processing circuits remains vital and their design challenging. Moreover, the emerging high-definition TV technology has created a new area for IC development, one with formidable signal processing requirements. The antialiasing filters needed for one proposed HDTV decoder motivated the research documented in this book. Sharply selective filters place tight constraints on the permitted excess phase shifts of their constituent circuits. Combined with stringent requirements for low distortion at video frequencies, these constraints challenge the IC filter designer. Integrated Video-Frequency Continuous-Time Filters: High-Performance Realizations in BiCMOS deals with what is arguably the mainstay of analog signal processing circuits. Prominent applications in computer disk-drive read channels, video receivers, rf circuits, and antialiasing and reconstruction in data converters testifies to their importance. Moreover, they are excellent benchmarks for more general analog signal processors. Bipolar and MOSFET transistors, freely combined at the lowest circuit levels, provide the designer with an opportunity to develop potent variations on the standard idioms. The book considers the general principles of BiCMOS circuit design, through to a demanding design problem. This case-study approach allows a concrete discussion of the justification for and practical trade-offs of each design decision. Audience: A reference work for experienced IC designers and a text for advanced IC design students.

Interconnect has become the dominating factor in determining system performance in nanometer technologies. This book is dedicated to this important subject. The primary purpose of this monograph is to provide insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits. In this monograph, the effects of wire size, spacing between wires, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap (near driver or receiver side), frequency, shields, direction of the signals, and wire width for both the aggressors and the victim wires on system performance and reliability is thoroughly investigated. Also, parameters like driver strength has been considered as several recent studies considered the simultaneous device and interconnect sizing. Crosstalk noise, as well as the impact of coupling on aggressor delay is analyzed. The pulse width of the crosstalk noise, which is of similar importance for circuit performance as the peak amplitude, is also analyzed. We have considered more parameters that can affect the signal integrity and presented a practical intensive simulation results. throughout the literature, presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. The practical aspects of the algorithms and models are explained with sufficient detail. It deeply investigates the most two effective parameters in layout optimization, spacing and shield insertion, that can affect both capacitive and inductive noise. Noise models needed for layouts with multi-layer multi-crosscoupling segments are investigated. Different post-layout optimization techniques are explained with complexity analysis and benchmarks tests are provided.

Synthesis of Finite State Machines: Logic Optimization is the second in a set of two monographs devoted to the synthesis of Finite State Machines (FSMs). The first volume, Synthesis of Finite State Machines: Functional Optimization, addresses functional optimization, whereas this one addresses logic optimization. The result of functional optimization is a symbolic description of an FSM which represents a sequential function chosen from a collection of permissible candidates. Logic optimization is the body of techniques for converting a symbolic description of an FSM into a hardware implementation. The mapping of a given symbolic representation into a two-valued logic implementation is called state encoding (or state assignment) and it impacts heavily area, speed, testability and power consumption of the realized circuit. The first part of the book introduces the relevant background, presents results previously scattered in the literature on the computational complexity of encoding problems, and surveys in depth old and new approaches to encoding in logic synthesis. The second part of the book presents two main results about symbolic minimization; a new procedure to find minimal two-level symbolic covers, under face, dominance and disjunctive constraints, and a unified frame to check encodability of encoding constraints and find codes of minimum length that satisfy them. The third part of the book introduces generalized prime implicants (GPIs), which are the counterpart, in symbolic minimization of two-level logic, to prime implicants in two-valued two-level minimization. GPIs enable the design of an exact procedure for two-level symbolic minimization, based on a covering step which is complicated by the need to guarantee encodability of the final cover. A new efficient algorithm to verify encodability of a selected cover is presented. If a cover is not encodable, it is shown how to augment it minimally until an encodable superset of GPIs is determined. To handle encodability the authors have extended the frame to satisfy encoding constraints presented in the second part. The covering problems generated in the minimization of GPIs tend to be very large. Recently large covering problems have been attacked successfully by representing the covering table with binary decision diagrams (BDD). In the fourth part of the book the authors introduce such techniques and extend them to the case of the implicit minimization of GPIs, where the encodability and augmentation steps are also performed implicitly. Synthesis of Finite State Machines: Logic Optimization will be of interest to researchers and professional engineers who work in the area of computer-aided design of integrated circuits.