This thesis explores a route to induce and control the structure formation process in thin films by the use of strong electric fields. We investigate, establish and apply the use of the electrohydrodynamic (EHD) lithography as a versatile patterning tool on the sub-micrometre and nanometre length scales for functional materials. Thin films are ubiquitous, they are found in nature and used in almost every aspect of daily life. While film instabilities are often undesirable in nature and technology, they can be utilized to produce structures by precisely controlling the destabilization of the film. EHD lithography utilizes instabilities induced by means of an electric field to fabricate periodic structures. EHD patterning is set to become a competitive candidate for low-cost lithographic technology for a number of applications. Herein, the applied potential of this lithographic process is explored by expanding its applicability to a broad range of materials and by a simultaneous patterning of multilayer systems or functional polymers yielding hierarchical architectures with novel functionalities.
EHD pattern formation enables for instance, the fabrication of multi-scale structured arrays as surface enhanced Raman scattering (SERS)-active platforms. Furthermore, crystalline and conductive polymers are patterned using the EHD approach and the underlying structure formation mechanisms are discussed. This extension towards functional material systems offers interesting prospects for potential applications. Findings of this thesis are very promising for use in optoelectronic devices.

As electronic designers pack more and more circuits onto a single chip to create increasingly complex devices, they run into a daunting obstacle: intermodulation distortion. This distortion occurs when are circuits are too closely placed together and their operating frequencies begin to interfere with each other. This manual addresses all aspects of intermodulation distortion. From the basics of circuit design, to cutting-edge techniques, it offers practitioners hands-on guidance for their challenging projects.

One of the most notable features of nanometer scale CMOS technology is the increasing magnitude of variability of the key device parameters affecting performance of integrated circuits. The growth of variability can be attributed to multiple factors, including the difficulty of manufacturing control, the emergence of new systematic variation-generating mechanisms, and most importantly, the increase in atomic-scale randomness, where device operation must be described as a stochastic process. In addition to wide-sense stationary stochastic device variability and temperature variation, existence of non-stationary stochastic electrical noise associated with fundamental processes in integrated-circuit devices represents an elementary limit on the performance of electronic circuits. In an attempt to address these issues, Stochastic Process Variation in Deep-Submicron CMOS: Circuits and Algorithms offers unique combination of mathematical treatment of random process variation, electrical noise and temperature and necessary circuit realizations for on-chip monitoring and performance calibration. The associated problems are addressed at various abstraction levels, i.e. circuit level, architecture level and system level. It therefore provides a broad view on the various solutions that have to be used and their possible combination in very effective complementary techniques for both analog/mixed-signal and digital circuits. The feasibility of the described algorithms and built-in circuitry has been verified by measurements from the silicon prototypes fabricated in standard 90 nm and 65 nm CMOS technology.

An emerging trend in the automobile industry is its convergence with information technology (IT). Indeed, it has been estimated that almost 90% of new automobile technologies involve IT in some form. "Smart" driving technologies that improve safety as well as "green" fuel technologies are quite representative of the convergence between IT and automobiles. The smart driving technologies include three key elements: sensing of driving environments, detection of objects and potential hazards and the generation of driving control signals including warning signals.

Although radar-based systems are primarily used for sensing the driving environments, the camera has gained importance in advanced driver assistance systems (ADAS).

This book covers system-on-a-chip (SoC) designs including both algorithms and hardware related with image sensing and object detection by using the camera for smart driving systems. It introduces a variety of algorithms such as lens correction, super resolution, image enhancement and object detections from the images captured by low-cost vehicle camera. This is followed by implementation issues such as SoC architecture, hardware accelerator, software development environment and reliability techniques for automobile vision systems.

This book is aimed for the new and practicing engineers in automotive and chip-design industries to provide some overall guidelines for the development of automotive vision systems.

It will also help graduate students understand and get started for the research work in this field."

This book explores energy efficiency techniques for high-performance computing (HPC) systems using power-management methods. Adopting a step-by-step approach, it describes power-management flows, algorithms and mechanism that are employed in modern processors such as Intel Sandy Bridge, Haswell, Skylake and other architectures (e.g. ARM). Further, it includes practical examples and recent studies demonstrating how modem processors dynamically manage wide power ranges, from a few milliwatts in the lowest idle power state, to tens of watts in turbo state. Moreover, the book explains how thermal and power deliveries are managed in the context this huge power range. The book also discusses the different metrics for energy efficiency, presents several methods and applications of the power and energy estimation, and shows how by using innovative power estimation methods and new algorithms modern processors are able to optimize metrics such as power, energy, and performance. Different power estimation tools are presented, including tools that break down the power consumption of modern processors at sub-processor core/thread granularity. The book also investigates software, firmware and hardware coordination methods of reducing power consumption, for example a compiler-assisted power management method to overcome power excursions. Lastly, it examines firmware algorithms for dynamic cache resizing and dynamic voltage and frequency scaling (DVFS) for memory sub-systems.

This book will provide readers with deep insight into the intriguing science of thermoelectric thin films. It serves as a fundamental information source on the techniques and methodologies involved in thermoelectric thin film growth, characterization and device processing. This book involves widespread contributions on several categories of thermoelectric thin films: oxides, chalcogenides, iodates, nitrides and polymers. This will serve as an invaluable resource for experts to consolidate their knowledge and will provide insight and inspiration to beginners wishing to learn about thermoelectric thin films. Provides a single-source reference on a wide spectrum of topics related to thermoelectric thin films, from organic chemistry to devices, from physical chemistry to applied physics, from synthesis to device implementation; Covers several categories of thermoelectric thin films based on different material approaches such as oxides, chalcogenides, iodates, nitrides and polymers; Discusses synthesis, characterization, and device processing of thermoelectric thin films, as well as the nanoengineering approach to tailor the properties of the used materials at the nanoscale level.

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

This book is based on a graduate course entitled, Ubiquitous Healthcare Circuits and Systems, that was given by one of the editors at his university. It includes an introduction and overview to the field of biomedical ICs and provides information on the current trends in research. The material focuses on the design of biomedical ICs rather than focusing on how to use prepared ICs.

The book provides a comprehensive description and implementation methodology for the Philips/NXP Aethereal/aelite Network-on-Chip (NoC). The presentation offers a systems perspective, starting from the system requirements and deriving and describing the resulting hardware architectures, embedded software, and accompanying design flow. Readers get an in depth view of the interconnect requirements, not centered only on performance and scalability, but also the multi-faceted, application-driven requirements, in particular composability and predictability. The book shows how these qualitative requirements are implemented in a state-of-the-art on-chip interconnect, and presents the realistic, quantitative costs.

Since process variation and chip performance uncertainties have become more pronounced as technologies scale down into the nanometer regime, accurate and efficient modeling or characterization of variations from the device to the architecture level have become imperative for the successful design of VLSI chips. This book provides readers with tools for variation-aware design methodologies and computer-aided design (CAD) of VLSI systems, in the presence of process variations at the nanometer scale. It presents the latest developments for modeling and analysis, with a focus on statistical interconnect modeling, statistical parasitic extractions, statistical full-chip leakage and dynamic power analysis considering spatial correlations, statistical analysis and modeling for large global interconnects and analog/mixed-signal circuits. Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits; Helps chip designers understand the potential and limitations of their design tools, improving their design productivity; Presents analysis of each algorithm with practical applications in the context of real circuit design; Includes numerical examples for the quantitative analysis and evaluation of algorithms presented. Provides readers with timely, systematic and comprehensive treatments of statistical modeling and analysis of VLSI systems with a focus on interconnects, on-chip power grids and clock networks, and analog/mixed-signal circuits; Helps chip designers understand the potential and limitations of their design tools, improving their design productivity; Presents analysis of each algorithm with practical applications in the context of real circuit design; Includes numerical examples for the quantitative analysis and evaluation of algorithms presented.

A survey of monolithic tunable semiconductor lasers, including applications in optical communication systems. The text discusses the underlying physics, operational principles and performance and applications of tunable laser diodes, covering tuning mechanisms, properties and laser structures.

This book provides an overview of and essential insights on invasive computing. Pursuing a comprehensive approach, it addresses proper concepts, invasive language constructs, and the principles of invasive hardware. The main focus is on the important topic of how to map task-parallel applications to future multi-core architectures including 1,000 or more processor units. A special focus today is the question of how applications can be mapped onto such architectures while not only taking into account functional correctness, but also non-functional execution properties such as execution times and security properties. The book provides extensive experimental evaluations, investigating the benefits of applying invasive computing and hybrid application mapping to give guarantees on non-functional properties such as timing, energy, and security. The techniques in this book are presented in a step-by-step manner, supported by examples and figures. All proposed ideas for providing guarantees on performance, energy consumption, and security are enabled by using the concept of invasive computing and the exclusive usage of resources.

This book explains the application of recent advances in computational intelligence - algorithms, design methodologies, and synthesis techniques - to the design of integrated circuits and systems. It highlights new biasing and sizing approaches and optimization techniques and their application to the design of high-performance digital, VLSI, radio-frequency, and mixed-signal circuits and systems. This second of two related volumes addresses digital and network designs and applications, with 12 chapters grouped into parts on digital circuit design, network optimization, and applications. It will be of interest to practitioners and researchers in computer science and electronics engineering engaged with the design of electronic circuits.

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

This work offers a practical, non-theoretical introduction to the principles, application and benefits of multi-sensor technology in smart weapon development, surveillance systems, and an increasing variety of non-military applications. It also provides an overview of MMW (Millimeter-Wave) and IR (infrared) sensor constraints, design principles, system alternatives and targeting applications.

This book is about formal veri?cation, that is, the use of mathematical reasoning to ensure correct execution of computing systems. With the increasing use of c- puting systems in safety-critical and security-critical applications, it is becoming increasingly important for our well-being to ensure that those systems execute c- rectly. Over the last decade, formal veri?cation has made signi?cant headway in the analysis of industrial systems, particularly in the realm of veri?cation of hardware. A key advantage of formal veri?cation is that it provides a mathematical guarantee of their correctness (up to the accuracy of formal models and correctness of r- soning tools). In the process, the analysis can expose subtle design errors. Formal veri?cation is particularly effective in ?nding corner-case bugs that are dif?cult to detect through traditional simulation and testing. Nevertheless, and in spite of its promise, the application of formal veri?cation has so far been limited in an ind- trial design validation tool ?ow. The dif?culties in its large-scale adoption include the following (1) deductive veri?cation using theorem provers often involves - cessive and prohibitive manual effort and (2) automated decision procedures (e. g. , model checking) can quickly hit the bounds of available time and memory. This book presents recent advances in formal veri?cation techniques and d- cusses the applicability of the techniques in ensuring the reliability of large-scale systems. We deal with the veri?cation of a range of computing systems, from - quential programsto concurrentprotocolsand pipelined machines.

Chip-integrated power management solutions are a must for ultra-low power systems. This enables not only the optimization of innovative sensor applications. It is also essential for integration and miniaturization of energy harvesting supply strategies of portable and autonomous monitoring systems. The book particularly addresses interfaces for energy harvesting, which are the key element to connect micro transducers to energy storage elements. Main features of the book are: - A comprehensive technology and application review, basics on transducer mechanics, fundamental circuit and control design, prototyping and testing, up to sensor system supply and applications. - Novel interfacing concepts - including active rectifiers, MPPT methods for efficient tracking of DC as well as AC sources, and a fully-integrated charge pump for efficient maximum AC power tracking at sub-100W ultra-low power levels. The chips achieve one of widest presented operational voltage range in standard CMOS technology: 0.44V to over 4.1V. - Two special chapters on analog circuit design - it studies benefits and obstacles on implemented chip prototypes with three goals: ultra- low power, wide supply voltage range, and integration with standard technologies. Alternative design approaches are pursued using bulk-input transistor stages in forward-bias operation for amplifiers, modulators, and references. - Comprehensive Appendix - with additional fundamental analysis, design and scaling guidelines, circuit implementation tables and dimensions, schematics, source code listings, bill of material, etc. The discussed prototypes and given design guidelines are tested with real vibration transducer devices. The intended readership is graduate students in advanced courses, academics and lecturers, R&D engineers.

Embedded systems applications that are either mission or safety-critical usually entail low- to mid- production volumes, require the rapid development of specific tasks, which are typically computing intensive, and are cost bounded. The adoption of re-configurable FPGAs in such application domains is constrained to the availability of suitable techniques to guarantee the dependability requirements entailed by critical applications. This book describes the challenges faced by designers when implementing a mission- or safety-critical application using re-configurable FPGAs and it details various techniques to overcome these challenges. In addition to an overview of the key concepts of re-configurable FPGAs, it provides a theoretical description of the failure modes that can cause incorrect operation of re-configurable FPGA-based electronic systems. It also outlines analysis techniques that can be used to forecast such failures and covers the theory behind solutions to mitigate fault effects. This book also reviews current technologies available for building re-configurable FPGAs, specifically SRAM-based technology and Flash-based technology. For each technology introduced, theoretical concepts presented are applied to real cases. Design techniques and tools are presented to develop critical applications using commercial, off-the-shelf devices, such as Xilinx Virtex FPGAs, and Actel ProASIC FPGAs. Alternative techniques based on radiation hardened FPGAs, such as Xilinx SIRF and Atmel ATF280 are also presented. This publication is an invaluable reference for anyone interested in understanding the technologies of re-configurable FPGAs, as well as designers developing critical applications based on these technologies.

This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems. It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.

This book discusses the design of multi-camera systems and their application to fields such as the virtual reality, gaming, film industry, medicine, automotive industry, drones, etc. The authors cover the basics of image formation, algorithms for stitching a panoramic image from multiple cameras, and multiple real-time hardware system architectures, in order to have panoramic videos. Several specific applications of multi-camera systems are presented, such as depth estimation, high dynamic range imaging, and medical imaging.

Simulation based on mathematical models plays a major role in computer aided design of integrated circuits (ICs). Decreasing structure sizes, increasing packing densities and driving frequencies require the use of refined mathematical models, and to take into account secondary, parasitic effects. This leads to very high dimensional problems which nowadays require simulation times too large for the short time-to-market demands in industry. Modern Model Order Reduction (MOR) techniques present a way out of this dilemma in providing surrogate models which keep the main characteristics of the device while requiring a significantly lower simulation time than the full model. With Model Reduction for Circuit Simulation we survey the state of the art in the challenging research field of MOR for ICs, and also address its future research directions. Special emphasis is taken on aspects stemming from miniturisations to the nano scale. Contributions cover complexity reduction using e.g., balanced truncation, Krylov-techniques or POD approaches. For semiconductor applications a focus is on generalising current techniques to differential-algebraic equations, on including design parameters, on preserving stability, and on including nonlinearity by means of piecewise linearisations along solution trajectories (TPWL) and interpolation techniques for nonlinear parts. Furthermore the influence of interconnects and power grids on the physical properties of the device is considered, and also top-down system design approaches in which detailed block descriptions are combined with behavioral models. Further topics consider MOR and the combination of approaches from optimisation and statistics, and the inclusion of PDE models with emphasis on MOR for the resulting partial differential algebraic systems. The methods which currently are being developed have also relevance in other application areas such as mechanical multibody systems, and systems arising in chemistry and to biology. The current number of books in the area of MOR for ICs is very limited, so that this volume helps to fill a gap in providing the state of the art material, and to stimulate further research in this area of MOR. Model Reduction for Circuit Simulation also reflects and documents the vivid interaction between three active research projects in this area, namely the EU-Marie Curie Action ToK project O-MOORE-NICE (members in Belgium, The Netherlands and Germany), the EU-Marie Curie Action RTN-project COMSON (members in The Netherlands, Italy, Germany, and Romania), and the German federal project System reduction in nano-electronics (SyreNe).

This book provides embedded software developers with techniques for programming heterogeneous Multi-Processor Systems-on-Chip (MPSoCs), capable of executing multiple applications simultaneously. It describes a set of algorithms and methodologies to narrow the software productivity gap, as well as an in-depth description of the underlying problems and challenges of today's programming practices. The authors present four different tool flows: A parallelism extraction flow for applications written using the C programming language, a mapping and scheduling flow for parallel applications, a special mapping flow for baseband applications in the context of Software Defined Radio (SDR) and a final flow for analyzing multiple applications at design time. The tool flows are evaluated on Virtual Platforms (VPs), which mimic different characteristics of state-of-the-art heterogeneous MPSoCs.

This book provides a systematic and unified methodology, including basic principles and reusable processes, for dynamic memory management (DMM) in embedded systems. The authors describe in detail how to design and optimize the use of dynamic memory in modern, multimedia and network applications, targeting the latest generation of portable embedded systems, such as smartphones. Coverage includes a variety of design and optimization topics in electronic design automation of DMM, from high-level software optimization to microarchitecture-level hardware support. The authors describe the design of multi-layer dynamic data structures for the final memory hierarchy layers of the target portable embedded systems and how to create a low-fragmentation, cost-efficient, dynamic memory management subsystem out of configurable components for the particular memory allocation and de-allocation patterns for each type of application. The design methodology described in this book is based on propagating constraints among design decisions from multiple abstraction levels (both hardware and software) and customizing DMM according to application-specific data access and storage behaviors.

This book explores the impacts of important material parameters on the electrical properties of indium arsenide (InAs) nanowires, which offer a promising channel material for low-power electronic devices due to their small bandgap and high electron mobility. Smaller diameter nanowires are needed in order to scale down electronic devices and improve their performance. However, to date the properties of thin InAs nanowires and their sensitivity to various factors were not known. The book presents the first study of ultrathin InAs nanowires with diameters below 10 nm are studied, for the first time, establishing the channel in field-effect transistors (FETs) and the correlation between nanowire diameter and device performance. Moreover, it develops a novel method for directly correlating the atomic-level structure with the properties of individual nanowires and their device performance. Using this method, the electronic properties of InAs nanowires and the performance of the FETs they are used in are found to change with the crystal phases (wurtzite, zinc-blend or a mix phase), the axis direction and the growth method. These findings deepen our understanding of InAs nanowires and provide a potential way to tailor device performance by controlling the relevant parameters of the nanowires and devices.

This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques.