Wave Pipelining: Theory and CMOS Implementation provides a coherent presentation of the theory of wave pipelined operation of digital circuits and discusses practical design techniques for the realization of wave pipelined circuits in CMOS technology. Wave pipeling is a timing methodology used in digital systems to enhance performance while conserving the number of data registers used. This is achieved by applying new data to the inputs of a combinatorial logic block before the previous outputs are available. In contrast to conventional pipelining, system performance is limited by differences in maximum and minimum circuit delay rather than maximum circuit delays. Realization of practical systems using this technique requires accurate system level and circuit level timing analysis. At the system level, timing constraints identifying valid regions of operation for correct clocking of wave pipelined circuits are presented. Both single stage and multiple stage systems including feedback are considered. At the circuit level, since performance is determined by the maximum circuit delay difference, highly accurate estimates of both maximum and minimum delays are needed. Thus, timing analysis based on traditional gate delay models is not sufficient. For CMOS circuits, data dependent delay models considering the effect of simultaneous multiple input switchings must be used. An algorithm using these delay models for accurate analysis of small to medium sized circuits is implemented in a prototype timing analyzer, XTV. Results are given for a set of benchmark circuits.

The purpose of this book is to provide a practical approach to managing security in FPGA designs for researchers and practitioners in the electronic design automation (EDA) and FPGA communities, including corporations, industrial and government research labs, and academics. This book combines theoretical underpinnings with a practical design approach and worked examples for combating real world threats. To address the spectrum of lifecycle and operational threats against FPGA systems, a holistic view of FPGA security is presented, from formal top level speci?cation to low level policy enforcement mechanisms, which integrates recent advances in the ?elds of computer security theory, languages, compilers, and hardware. The net effect is a diverse set of static and runtime techniques that, working in coope- tion, facilitate the composition of robust, dependable, and trustworthy systems using commodity components. We wish to acknowledge the many people who helped us ensure the success of ourworkonrecon?gurablehardwaresecurity.Inparticular, wewishtothankAndrei Paun and Jason Smith of Louisiana Tech University for providing us with a Lin- compatible version of Grail+. We also wish to thank those who gave us comments on drafts of this book, including Marco Platzner of the University of Paderborn, and Ali Irturk and Jason Oberg of the University of California, San Diego. This research was funded in part by National Science Foundation Grant CNS-0524771 and NSF Career Grant CCF-0448654

Application Specific Processors is written for use by engineers who are developing specialized systems (application specific systems). Traditionally, most high performance signal processors have been realized with application specific processors. The explanation is that application specific processors can be tailored to exactly match the (usually very demanding) application requirements. The result is that no processing power' is wasted for unnecessary capabilities and maximum performance is achieved. A disadvantage is that such processors have been expensive to design since each is a unique design that is customized to the specific application. In the last decade, computer-aided design systems have been developed to facilitate the development of application specific integrated circuits. The success of such ASIC CAD systems suggests that it should be possible to streamline the process of application specific processor design. Application Specific Processors consists of eight chapters which provide a mixture of techniques and examples that relate to application specific processing. The inclusion of techniques is expected to suggest additional research and to assist those who are faced with the requirement to implement efficient application specific processors. The examples illustrate the application of the concepts and demonstrate the efficiency that can be achieved via application specific processors. The chapters were written by members and former members of the application specific processing group at the University of Texas at Austin. The first five chapters relate to specific arithmetic which often is the key to achieving high performance in application specific processors. The next two chapters focus on signal processing systems, and the final chapter examines the interconnection of possibly disparate elements to create systems.

High-Resolution IF-to-Baseband SigmaDelta ADC for Car Radios addresses the theory, system level design and circuit implementation of a high-resolution continuous-time IF-to-baseband quadrature SigmaDelta ADC. The target application of this ADC is in AM/FM/IBOC car radios. The ADC achieves a dynamic range of 118dB, which eliminates the need for an IF VGA or AM channel filter in car radios. The author is very well known within the Analog Circuits community.

Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips discusses architectures, circuits and procedures for the optimum design of bandpass sigma-delta (SD) A/D interfaces for mixed-signal chips in standard CMOS technologies. The book differs from others in the very detailed and in-depth coverage of switched-current (SI) errors, which supports the design of high performance SI chips. The book starts with a tutorial presentation of the fundamentals of bandpass SD converters, their applications in communications and their most common architectures. It then presents the basic SI building blocks required for their implementation and analyzes in great detail the operation of these blocks. The influence of SI errors on the performance of the SD modulators (SDMs) is also studied. The outcome is a unique set of models which can be employed with a double purpose: namely, to support iterative procedures employed in mapping specifications onto design parameters; and to allow for accurate behavioural time-domain simulation using MATLAB-like tools. The book is completed with two case studies corresponding to modulators for AM digital radio receivers.
The analyses, models and procedures in the book support the design of SI front-ends with performance indexes comparable to those of switched-capacitor circuits, which makes a significant difference as compared to previous works in the area of SI circuits. Together with a detailed revision of the SI literature, the book presents practical recipes on how to get the maximum performance from SI circuits, and illustrates them by means of two case study chips in CMOS submicron technologies. These prototypes constitute the first reported IC realizations of SI bandpass SDMs.
Systematic Design of CMOS Switched-Current Bandpass Sigma-Delta Modulators for Digital Communication Chips contains highly valuable and unique information to be used as a reference by designers of the analog front-end of mixed-signal chips. The models presented in the book will help these designers to increase their productivity. The tutorial, comprehensive coverage of all issues associated with bandpass sigma-delta converters makes the book very well suited for graduate courses. Finally, the very detailed coverage of errors and trade-offs in the operation of switched-current circuits will be found invaluable by teachers of undergraduate analog design courses.

This book covers the fundamental principles behind the design of ultra-low power radios and how they can form networks to facilitate a variety of applications within healthcare and environmental monitoring, since they may operate for years off a small battery or even harvest energy from the environment. These radios are distinct from conventional radios in that they must operate with very constrained resources and low overhead. This book provides a thorough discussion of the challenges associated with designing radios with such constrained resources, as well as fundamental design concepts and practical approaches to implementing working designs. Coverage includes integrated circuit design, timing and control considerations, fundamental theory behind low power and time domain operation, and network/communication protocol considerations.

This book focuses on the design of a Mega-Gray (a standard unit of total ionizing radiation) radiation-tolerant ps-resolution time-to-digital converter (TDC) for a light detection and ranging (LIDAR) system used in a gamma-radiation environment. Several radiation-hardened-by-design (RHBD) techniques are demonstrated throughout the design of the TDC and other circuit techniques to improve the TDC's resolution in a harsh environment are also investigated. Readers can learn from scratch how to design a radiation-tolerant IC. Information regarding radiation effects, radiation-hardened design techniques and measurements are organized in such a way that readers can easily gain a thorough understanding of the topic. Readers will also learn the design theory behind the newly proposed delta-sigma TDC. Readers can quickly acquire knowledge about the design of radiation-hardened bandgap voltage references and low-jitter relaxation oscillators, which are introduced in the content from a designer's perspective. * Discusses important aspects of radiation-tolerant analog IC design, including realistic applications and radiation effects on ICs; * Demonstrates radiation-hardened-by-design techniques through a design-test-radiation assessment practice; * Describes a new type of Time-to-Digital (TDC) converter designed for radiation-tolerant application; * Explains the design and measurement of all functional blocks (e.g., bandgap reference, relaxation oscillator) in the TDC.

Asynchronous Circuit Design for VLSI Signal Processing is a collection of research papers on recent advances in the area of specification, design and analysis of asynchronous circuits and systems. This interest in designing digital computing systems without a global clock is prompted by the ever growing difficulty in adopting global synchronization as the only efficient means to system timing. Asynchronous circuits and systems have long held interest for circuit designers and researchers alike because of the inherent challenge involved in designing these circuits, as well as developing design techniques for them. The frontier research in this area can be traced back to Huffman's publications The Synthesis of Sequential Switching Circuits' in 1954 followed by Unger's book, Asynchronous Sequential Switching Circuits' in 1969 where a theoretical foundation for handling logic hazards was established. In the last few years a growing number of researchers have joined force in unveiling the mystery of designing correct asynchronous circuits, and better yet, have produced several alternatives in automatic synthesis and verification of such circuits. This collection of research papers represents a balanced view of current research efforts in the design, synthesis and verification of asynchronous systems.

This book describes how engineers can make optimum use of the two industry standard analysis/design tools, SystemC and SystemC-AMS. The authors use a system-level design approach, emphasizing how SystemC and SystemC-AMS features can be exploited most effectively to analyze/understand a given electronic system and explore the design space. The approach taken by this book enables system engineers to concentrate on only those SystemC/SystemC-AMS features that apply to their particular problem, leading to more efficient design. The presentation includes numerous, realistic and complete examples, which are graded in levels of difficulty to illustrate how a variety of systems can be analyzed with these tools.

Temperature has been always considered as an appreciable magnitude to detect failures in electric systems. Abnormal status of this variable, both too high and too low, is sign of abnormal behavior in electronic systems. In Thermal Testing of Integrated Circuits the authors present the feasibility to consider temperature as an observable for testing purposes. The coupling of circuits through heat is inherent to the solid-state nature and the inspection of temperature does not interact with Under Test Circuits or Systems, something that does not happen when voltage or current observable are used. In the book the basis of heat propagation, heat conducting mechanisms and temperature sensitivity of semiconductors are focused with a full coverage of the state of the art. We usually have the idea that all the heating processes are slow, which is true in the macroscopic world, but is not in the case of integrated circuits where the reduced size and amount of material and the really high conductivity of substrates make the thermal testing a promising technique. CMOS and BICMOS temperature sensors for built-in thermal testing are presented in the book. The application of temperature as testing magnitude for both on-line and off-line, analog or digital, on-chip or off-chip are considered. The temperature sensing has an inherent directional capability that can be used as an element for localizing failures, so the technique has interesting diagnosis capabilities as well.

This book, written by experts in the field, is based on the latest research on the analysis and synthesis of switched time-delay systems. It covers the stability, filtering, fault detection and control problems, which are studied using the average dwell time approach. It presents both the continuous-time and discrete-time systems and provides useful insights and methods, as well as practical algorithms that can be considered in other complex systems, such as neuron networks and genetic regulatory networks, making it a valuable resource for researchers, scientists and engineers in the field of system sciences and control communities.

This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical sensors.

Operational Amplifier Speed and Accuracy Improvement proposes a new methodology for the design of analog integrated circuits. The usefulness of this methodology is demonstrated through the design of an operational amplifier. This methodology consists of the following iterative steps: description of the circuit functionality at a high level of abstraction using signal flow graphs; equivalent transformations and modifications of the graph to the form where all important parameters are controlled by dedicated feedback loops; and implementation of the structure using a library of elementary cells. Operational Amplifier Speed and Accuracy Improvement shows how to choose structures and design circuits which improve an operational amplifier's important parameters such as speed to power ratio, open loop gain, common-mode voltage rejection ratio, and power supply rejection ratio. The same approach is used to design clamps and limiting circuits which improve the performance of the amplifier outside of its linear operating region, such as slew rate enhancement, output short circuit current limitation, and input overload recovery.

This book introduces simulation tools and strategies for complex systems of solid-state-drives (SSDs) which consist of a flash multi-core microcontroller plus NAND flash memories. It provides a broad overview of the most popular simulation tools, with special focus on open source solutions. VSSIM, NANDFlashSim and DiskSim are benchmarked against performances of real SSDs under different traffic workloads. PROs and CONs of each simulator are analyzed, and it is clearly indicated which kind of answers each of them can give and at a what price. It is explained, that speed and precision do not go hand in hand, and it is important to understand when to simulate what, and with which tool. Being able to simulate SSD's performances is mandatory to meet time-to-market, together with product cost and quality. Over the last few years the authors developed an advanced simulator named "SSDExplorer" which has been used to evaluate multiple phenomena with great accuracy, from QoS (Quality Of Service) to Read Retry, from LDPC Soft Information to power, from Flash aging to FTL. SSD simulators are also addressed in a broader context in this book, i.e. the analysis of what happens when SSDs are connected to the OS (Operating System) and to the end-user application (for example, a database search). The authors walk the reader through the full simulation flow of a real system-level by combining SSD Explorer with the QEMU virtual platform. The reader will be impressed by the level of know-how and the combination of models that such simulations are asking for.

This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit's performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.

"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks."
- Stuart Swan

With the increased efforts of the analog design community to integrate analog high-frequency front-ends for telecommunications, there has been heightened interest in the behaviour of nonlinear circuits since this can cause considerable degradation of signals. In analog integrated circuits at lower frequencies, such as filters, nonlinear behaviour limits the dynamic range. Analog integrated circuit designers often lack insight into nonlinear circuit behaviour. Indeed, designers are trained to reason in linear or linearized circuits but not in nonlinear ones. Numerical circuit simulations of nonlinear circuit behavior do not provide enough insight to the designer. Distortion Analysis of Analog Integrated Circuits, with a foreword by Robert G. Meyer, provides both qualitative and quantitative insight into the nonlinear behavior of analog integrated circuits at low and high frequencies. General techniques to suppress nonlinear behavior such as pre-distortion, linear and nonlinear feedback are explained in detail and illustrated with realistic examples. In this way the book fills the gap between the theory of nonlinear systems and practical analog integrated circuits. Distortion Analysis of Analog Integrated Circuits provides the reader with an in-depth analysis of elementary transistor stages, both CMOS and bipolar, as well as an analysis of several larger circuits. Hereby use is made of advanced transistor models that are also discussed in the book. The analyses take into account many more effects than in existing publications, thanks to the use of a calculation method that yields closed-form expressions for nonlinear behavior. These expressions are interpreted and illustrated withrealistic numerical examples. Distortion Analysis of Analog Integrated Circuits is essential reading for practicing analog and mixed-signal design engineers and researchers in the field. It is also suitable as a text for an advanced course on the subject. From the foreword: I am sure that the analog circuit design community will [...] welcome this work by Dr. Wambacq and Prof. Sansen as a major contribution to the analog circuit design literature in the area of distortion analysis of electronic circuits. I am personally looking forward to having a copy readily available for reference when designing integrated circuits for communication systems.' Robert G. Meyer, Professor, Electrical Engineering and Computer Sciences, University of California, Berkeley.

Explains how to use low power design in an automated design flow, and examine the design time and performance trade-offs

Includes the latest tools and techniques for low power design applied in an ASIC design flow

Focuses on low power in an automated design methodology, a much neglected area

Written by an author with extensive practical experience of applying the techniques, this book is aimed at advanced students and researchers as well as professional design engineers. The text focuses on finite impulse response (FIR) filter structures and on infinite impulse response (IIR) SC filters which simulate classical lossless circuits . It includes coverage of the so-called pseudo-lossless SC circuits and especially multirate SC circuits with recovery of the effective pseudo-energy. There is also discussion of other promising approaches to the design of SC circuits; special attention has been paid to the analysis of multirate and multiphase SC circuits using signal flow graphs.

Provides coverage of the most efficient and effective methods of network analysis optimization and synthesis. A step-by-step guide to every aspect of the RF and microwave circuit design process - starting with a set of specifications and ending with hardware that performs as modeled the first time.

Digital phase locked loops are critical components of many communication, signal processing and control systems. This exciting new book covers various types of digital phase lock loops. It presents a comprehensive coverage of a new class of digital phase lock loops called the time delay tanlock loop (TDTL). It also details a number of architectures that improve the performance of the TDTL through adaptive techniques that overcome the conflicting requirements of the locking rage and speed of acquisition. These requirements are of paramount importance in many applications including wireless communications, consumer electronics and others. Digital Phase Lock Loops then illustrates the process of converting the TDTL class of digital phase lock loops for implementation on an FPGA-based reconfigurable system. These devices are being utilized in software-defined radio, DSP-based designs and many other communication and electronic systems to implement complex high-speed algorithms. Their flexibility and reconfigurability facilitate rapid prototyping, on-the-fly upgradeability, and code reuse with minimum effort and complexity. from the reconfigurable implementations are compared with those obtained through simulations with MATLAB/Simulink. The material in this book will be valuable to researchers, graduate students, and practicing engineers.

Debugging becomes more and more the bottleneck to chip design productivity, especially while developing modern complex integrated circuits and systems at the Electronic System Level (ESL). Today, debugging is still an unsystematic and lengthy process. Here, a simple reporting of a failure is not enough, anymore. Rather, it becomes more and more important not only to find many errors early during development but also to provide efficient methods for their isolation. In Debugging at the Electronic System Level the state-of-the-art of modeling and verification of ESL designs is reviewed. There, a particular focus is taken onto SystemC. Then, a reasoning hierarchy is introduced. The hierarchy combines well-known debugging techniques with whole new techniques to improve the verification efficiency at ESL. The proposed systematic debugging approach is supported amongst others by static code analysis, debug patterns, dynamic program slicing, design visualization, property generation, and automatic failure isolation. All techniques were empirically evaluated using real-world industrial designs. Summarized, the introduced approach enables a systematic search for errors in ESL designs. Here, the debugging techniques improve and accelerate error detection, observation, and isolation as well as design understanding.

Device and Circuit Cryogenic Operation for Low Temperature Electronics is a first in reviewing the performance and physical mechanisms of advanced devices and circuits at cryogenic temperatures that can be used for many applications. The first two chapters cover bulk silicon and SOI MOSFETs. The electronic transport in the inversion layer, the influence of impurity freeze-out, the special electrical properties of SOI structures, the device reliability and the interest of a low temperature operation for the ultimate integration of silicon down to nanometer dimensions are described. The next two chapters deal with Silicon-Germanium and III-V Heterojunction Bipolar Transistors, as well as III-V High Electron Mobility Transistors (HEMT). The basic physics of the SiGe HBT and its unique cryogenic capabilities, the optimization of such bipolar devices, and the performance of SiGe HBT BiCMOS technology at liquid nitrogen temperature are examined. The physical effects in III-V semiconductors at low temperature, the HEMT and HBT static, high frequency and noise properties, and the comparison of various cooled III-V devices are also addressed. The next chapter treats quantum effect devices made of silicon materials. The major quantum effects at low temperature, quantum wires, quantum dots as well as single electron devices and applications are investigated. The last chapter overviews the performances of cryogenic circuits and their applications. The low temperature properties and performance of inverters, multipliers, adders, operational amplifiers, memories, microprocessors, imaging devices, circuits and systems, sensors and read-out circuits are analyzed. Device and Circuit Cryogenic Operation for Low Temperature Electronics is useful for researchers, engineers, Ph.D. and M.S. students working in the field of advanced electron devices and circuits, new semiconductor materials, and low temperature electronics and physics.

Conceptual Design of Multichip Modules and Systems treats activities which take place at the conceptual and specification level of the design of complex multichip systems. These activities include the formalization of design knowledge (information modeling), tradeoff analysis, partitioning, and decision process capture. All of these functions occur prior to the traditional CAD activities of synthesis and physical design. Inherent in the design of electronic modules are tradeoffs which must be understood before feasible technology, material, process, and partitioning choices can be selected. The lack of a complete set of technology information is an especially serious problem in the packaging and interconnect field since the number of technologies, process, and materials is substantial and selecting optimums is arduous and non-trivial if one truly wants a balance in cost and performance. Numerous tradeoff and design decisions have to be made intelligently and quickly at the beginning of the design cycle before physical design work begins. These critical decisions, made within the first 10% of the total design cycle, ultimately define up to 80% of the final product cost. Conceptual Design of Multichip Modules and Systems lays the groundwork for concurrent estimation level analysis including size, routing, electrical performance, thermal performance, cost, reliability, manufacturability, and testing. It will be useful both as a reference for system designers and as a text for those wishing to gain a perspective on the nature of packaging and interconnect design, concurrent engineering, computer-aided design, and system synthesis.

Chemical mechanical planarization, or chemical mechanical polishing as it is simultaneously referred to, has emerged as one of the critical processes in semiconductor manufacturing and in the production of other related products and devices, MEMS for example. Since its introduction some 15+ years ago CMP, as it is commonly called, has moved steadily into new and challenging areas of semiconductor fabrication. Demands on it for consistent, efficient and cost-effective processing have been steady. This has continued in the face of steadily decreasing feature sizes, impressive increases in wafer size and a continuing array of new materials used in devices today. There are a number of excellent existing references and monographs on CMP in circulation and we defer to them for detailed background information. They are cited in the text. Our focus here is on the important area of process mod els which have not kept pace with the tremendous expansion of applications of CMP. Preston's equation is a valuable start but represents none of the subtleties of the process. Specifically, we refer to the development of models with sufficient detail to allow the evaluation and tradeoff of process inputs and parameters to assess impact on quality or quantity of production. We call that an "integrated model" and, more specifically, we include the important role of the mechanical elements of the process."