This book provides embedded software developers with techniques for programming heterogeneous Multi-Processor Systems-on-Chip (MPSoCs), capable of executing multiple applications simultaneously. It describes a set of algorithms and methodologies to narrow the software productivity gap, as well as an in-depth description of the underlying problems and challenges of today's programming practices. The authors present four different tool flows: A parallelism extraction flow for applications written using the C programming language, a mapping and scheduling flow for parallel applications, a special mapping flow for baseband applications in the context of Software Defined Radio (SDR) and a final flow for analyzing multiple applications at design time. The tool flows are evaluated on Virtual Platforms (VPs), which mimic different characteristics of state-of-the-art heterogeneous MPSoCs.

This book provides a systematic and unified methodology, including basic principles and reusable processes, for dynamic memory management (DMM) in embedded systems. The authors describe in detail how to design and optimize the use of dynamic memory in modern, multimedia and network applications, targeting the latest generation of portable embedded systems, such as smartphones. Coverage includes a variety of design and optimization topics in electronic design automation of DMM, from high-level software optimization to microarchitecture-level hardware support. The authors describe the design of multi-layer dynamic data structures for the final memory hierarchy layers of the target portable embedded systems and how to create a low-fragmentation, cost-efficient, dynamic memory management subsystem out of configurable components for the particular memory allocation and de-allocation patterns for each type of application. The design methodology described in this book is based on propagating constraints among design decisions from multiple abstraction levels (both hardware and software) and customizing DMM according to application-specific data access and storage behaviors.

FPGAs (Field-Programmable Gate Arrays) can be found in applications such as smart phones, mp3 players, medical imaging devices, and for aerospace and defense technology. FPGAs consist of logic blocks and programmable interconnects. This allows an engineer to start with a blank slate and program the FPGA for a specific task, for instance, digital signal processing, or a specific device, for example, a software-defined radio. Due to the short time to market and ability to reprogram to fix bugs without having to respin FPGAs are in increasingly high demand.
This book is for the engineer that has not yet had any experience with this electrifying and growing field. The complex issue of FPGA design is broken down into four distinct phases - Design / Synthesis / Simulation / Place & Route. Numerous step-by-step examples along with source code accompany the discussion. A brief primer of one of the popular FPGA and hardware languages, VHDL, is incorporated for a simple yet comprehensive learning tool. While a general technology background is assumed, no direct hardware development understanding is needed. Also, included are details on tool-set up, verifaction techniques, and test benches. Reference material consists of a quick reference guide, reserved words, and common VHDL/FPGA terms.
Learn how to design and develop FPGAs -- no prior experience necessary Breaks down the complex design and development of FPGAs into easy-to-learn building blocksContains examples, helpful tips, and step-by-step tutorials for synthesis, implementation, simulation, and programming phases

This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques.

This book covers key concepts in the design of 2D and 3D Network-on-Chip interconnect. It highlights design challenges and discusses fundamentals of NoC technology, including architectures, algorithms and tools. Coverage focuses on topology exploration for both 2D and 3D NoCs, routing algorithms, NoC router design, NoC-based system integration, verification and testing, and NoC reliability. Case studies are used to illuminate new design methodologies.

This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desired number of processing elements (PEs) or region within a TCPA exclusively for an application according to performance requirements. It not only presents models for implementing invasion strategies in hardware, but also proposes two distinct design flavors for dedicated hardware components to support invasion control on TCPAs.

This book provides a comprehensive guide to the design of sustainable and green computing systems (GSC). Coverage includes important breakthroughs in various aspects of GSC, including multi-core architectures, interconnection technology, data centers, high performance computing (HPC), and sensor networks. The authors address the challenges of power efficiency and sustainability in various contexts, including system design, computer architecture, programming languages, compilers and networking.

These are the proceedings of the 20th international conference on domain decomposition methods in science and engineering. Domain decomposition methods are iterative methods for solving the often very large linearor nonlinear systems of algebraic equations that arise when various problems in continuum mechanics are discretized using finite elements. They are designed for massively parallel computers and take the memory hierarchy of such systems in mind. This is essential for approaching peak floating point performance. There is an increasingly well developed theory whichis having a direct impact on the development and improvements of these algorithms.

This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book's chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. * Examines how to optimize the architecture of hardware design for error correcting codes; * Presents error correction codes from theory to optimized architecture for the current and the next generation standards; * Provides coverage of industrial user needs advanced error correcting techniques. Advanced Hardware Design for Error Correcting Codes includes a foreword by Claude Berrou.

This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets.

This book is about security in embedded systems and it provides an authoritative reference to all aspects of security in system-on-chip (SoC) designs. The authors discuss issues ranging from security requirements in SoC designs, definition of architectures and design choices to enforce and validate security policies, and trade-offs and conflicts involving security, functionality, and debug requirements. Coverage also includes case studies from the "trenches" of current industrial practice in design, implementation, and validation of security-critical embedded systems. Provides an authoritative reference and summary of the current state-of-the-art in security for embedded systems, hardware IPs and SoC designs; Takes a "cross-cutting" view of security that interacts with different design and validation components such as architecture, implementation, verification, and debug, each enforcing unique trade-offs; Includes high-level overview, detailed analysis on implementation, and relevant case studies on design/verification/debug issues related to IP/SoC security.

Given the widespread use of real-time multitasking systems, there are tremendous optimization opportunities if reconfigurable computing can be effectively incorporated while maintaining performance and other design constraints of typical applications. The focus of this book is to describe the dynamic reconfiguration techniques that can be safely used in real-time systems. This book provides comprehensive approaches by considering synergistic effects of computation, communication as well as storage together to significantly improve overall performance, power, energy and temperature."

Modern multimedia systems are becoming increasingly multiprocessor and heterogeneous to match the high performance and low power demands placed on them by the large number of applications. The concurrent execution of these applications causes interference and unpredictability in the performance of these systems. In Multimedia Multiprocessor Systems, an analysis mechanism is presented to accurately predict the performance of multiple applications executing concurrently. With high consumer demand the time-to-market has become significantly lower. To cope with the complexity in designing such systems, an automated design-flow is needed that can generate systems from a high-level architectural description such that they are not error-prone and consume less time. Such a design methodology is presented for multiple use-cases -- combinations of active applications. A resource manager is also presented to manage the various resources in the system, and to achieve the goals of performance prediction, admission control and budget enforcement.

Dynamically Reconfigurable Systems is the first ever to focus on the emerging field of Dynamically Reconfigurable Computing Systems. While programmable logic and design-time configurability are well elaborated and covered by various texts, this book presents a unique overview over the state of the art and recent results for dynamic and run-time reconfigurable computing systems.

Reconfigurable hardware is not only of utmost importance for large manufacturers and vendors of microelectronic devices and systems, but also a very attractive technology for smaller and medium-sized companies. Hence, Dynamically Reconfigurable Systems also addresses researchers and engineers actively working in the field and provides them with information on the newest developments and trends in dynamic and run-time reconfigurable systems.

This book is the fifth volume of the CoreGRID series. Organized jointly with the Euro-Par 2007 conference, The CoreGRID Symposium intends to become the premiere European event on Grid Computing. The aim of this symposium is to strengthen and advance scientific and technological excellence in the area of Grid and Peer-to-Peer Computing. The book includes all aspects of Grid Computing including service infrastructure. It is designed for a professional audience composed of researchers and practitioners in industry. This volume is also suitable for advanced-level students in computer science.

Fundamental Problems in Computing is in honor of Professor Daniel J. Rosenkrantz, a distinguished researcher in Computer Science. Professor Rosenkrantz has made seminal contributions to many subareas of Computer Science including formal languages and compilers, automata theory, algorithms, database systems, very large scale integrated systems, fault-tolerant computing and discrete dynamical systems. For many years, Professor Rosenkrantz served as the Editor-in-Chief of the Journal of the Association for Computing Machinery (JACM), a very prestigious archival journal in Computer Science. His contributions to Computer Science have earned him many awards including the Fellowship from ACM and the ACM SIGMOD Contributions Award.

Efficient design of embedded processors plays a critical role in embedded systems design. Processor description languages and their associated specification, exploration and rapid prototyping methodologies are used to find the best possible design for a given set of applications under various design constraints, such as area, power and performance.
This book is the first, comprehensive survey of modern architecture description languages and will be an invaluable reference for embedded system architects, designers, developers, and validation engineers. Readers will see that the use of particular architecture description languages will lead to productivity gains in designing particular (application-specific) types of embedded processors.
* Comprehensive coverage of all modern architecture description languages... use the right ADL to design your processor to fit your application;
* Most up-to-date information available about each architecture description language from the developers...save time chasing down reliable documentation;
* Describes how each architecture desccription language enables key design automation tasks, such as simulation, synthesis and testing...fit the ADL to your design cycle;

This book provides a comprehensive overview of key technologies being used to address challenges raised by continued device scaling and the extending gap between memory and central processing unit performance. Authors discuss in detail what are known commonly as "More than Moore" (MtM), technologies, which add value to devices by incorporating functionalities that do not necessarily scale according to "Moore's Law". Coverage focuses on three key technologies needed for efficient power management and cost per performance: novel memories, 3D integration and photonic on-chip interconnect.

This book provides a comprehensive description of the architetural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp of the broader problem deffinition and solution space, this book also delves into the physics of soft errors and reviews current circuit and software mitigation techniques.
TABLE OF CONTENTS
Chapter 1: Introduction
Chapter 2: Device- and Circuit-Level Modeling, Measurement, and Mitigation
Chapter 3: Architectural Vulnerability Analysis
Chapter 4: Advanced Architectural Vulnerability Analysis
Chapter 5: Error Coding Techniques
Chapter 6: Fault Detection via Redundant Execution
Chapter 7: Hardware Error Recovery
Chapter 8: Software Detection and Recovery
* Helps readers build-in fault tolerance to the billions of microchips produced each year, all of which are subject to soft errors
* Shows readers how to quantify their soft error reliability
* Provides state-of-the-art techniques to protect against soft errors

This volume gives the latest developments in on the mechanisms of cancer cell resistance to apoptotic stimuli, which eventually result in cancer progression and metastasis. One of the main challenges in cancer research is to develop new therapies to combat resistant tumors. The development of new effective therapies will be dependent on delineating the biochemical, molecular, and genetic mechanisms that regulate tumor cell resistance to cytotoxic drug-induced apoptosis. These mechanisms should reveal gene products that directly regulate resistance in order to develop new drugs that target these resistance factors and such new drugs may either be selective or common to various cancers. If successful, new drugs may not be toxic and may be used effectively in combination with subtoxic conventional drugs to achieve synergy and to reverse tumor cell resistance. The research developments presented in this book can be translated to produce better clinical responses to resistant tumors.

This book provides an invaluable primer on the techniques utilized in the design of low power digital semiconductor devices. Readers will benefit from the hands-on approach which starts form the ground-up, explaining with basic examples what power is, how it is measured and how it impacts on the design process of application-specific integrated circuits (ASICs). The authors use both the Unified Power Format (UPF) and Common Power Format (CPF) to describe in detail the power intent for an ASIC and then guide readers through a variety of architectural and implementation techniques that will help meet the power intent. From analyzing system power consumption, to techniques that can be employed in a low power design, to a detailed description of two alternate standards for capturing the power directives at various phases of the design, this book is filled with information that will give ASIC designers a competitive edge in low-power design.

The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.
- Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
- Views of FPGA programming beyond Verilog/VHDL
- Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways