This book examines some of the underlying processes behind different forms of information management, including how we store information in our brains, the impact of new technologies such as computers and robots on our efficiency in storing information, and how information is stored in families and in society. The editors brought together experts from a variety of disciplines. While it is generally agreed that information reduces uncertainties and that the ability to store it safely is of vital importance, these authors are open to different meanings of "information": computer science considers the bit as the information block; neuroscience emphasizes the importance of information as sensory inputs that are processed and transformed in the brain; theories in psychology focus more on individual learning and on the acquisition of knowledge; and finally sociology looks at how interpersonal processes within groups or society itself come to the fore. The book will be of value to researchers and students in the areas of information theory, artificial intelligence, and computational neuroscience.

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

This volume gives an overview of the state-of-the-art with respect to the development of all types of parallel computers and their application to a wide range of problem areas.

The international conference on parallel computing ParCo97 (Parallel Computing 97) was held in Bonn, Germany from 19 to 22 September 1997. The first conference in this biannual series was held in 1983 in Berlin. Further conferences were held in Leiden (The Netherlands), London (UK), Grenoble (France) and Gent (Belgium).

From the outset the aim with the ParCo (Parallel Computing) conferences was to promote the application of parallel computers to solve real life problems. In the case of ParCo97 a new milestone was reached in that more than half of the papers and posters presented were concerned with application aspects. This fact reflects the coming of age of parallel computing.

Some 200 papers were submitted to the Program Committee by authors from all over the world. The final programme consisted of four invited papers, 71 contributed scientific/industrial papers and 45 posters. In addition a panel discussion on Parallel Computing and the Evolution of Cyberspace was held. During and after the conference all final contributions were refereed. Only those papers and
posters accepted during this final screening process are included in this volume.

The practical emphasis of the conference was accentuated by an industrial exhibition where companies demonstrated the newest developments in parallel processing equipment and software. Speakers from participating companies presented papers in industrial sessions in which new developments in parallel computing were reported.

As the demand for digital communication networks has increased, so have the challenges in network component design. To meet ever-escalating performance, flexibility, and economy requirements, the networking industry has opted to build products around network processors. These new chips range from task-specific processors, such as classification and encryption engines, to more general-purpose packet or communications processors. Programmable yet application-specific, their designs are tailored to efficiently implement communications applications such as routing, protocol analysis, voice and data convergence, firewalls, VPNs, and QoS.

Network processor design is an emerging field with issues and opportunities both numerous and formidable. To help meet this challenge, the editors of this volume created the first Workshop on Network Processors, a forum for scientists and engineers from academia and industry to discuss their latest research in the architecture, design, programming, and use of these devices. In addition to including the results of the Workshop in this volume, the editors also present specially commissioned material from practicing designers, who discuss their companies' latest network processors. "Network Processor Design: Issues and Practices" is an essential reference on network processors for graduate students, researchers, and practicing designers.
* Includes contributions from major academic and industrial research labs including Aachen University of Technology; Cisco Systems; Infineon Technologies; Intel Corp.; North Carolina State University; Swiss Federal Institute of Technology; University of California, Berkeley; University of Dortmund; University of Washington; and Washington University.
* Examines the latest network processors from Agere Systems, Cisco, IBM, Intel, Motorola, Sierra Inc., and TranSwitch.

Modern applications of logic, in mathematics, theoretical computer science, and linguistics, require combined systems involving many different logics working together. In this book the author offers a basic methodology for combining - or fibring - systems. This means that many existing complex systems can be broken down into simpler components, hence making them much easier to manipulate.

Unlike so many books that focus on how to use Linux, Linux and the Unix Philosophy explores the "way of thinking that is Linux" and why Linux is a superior implementation of this highly capable operating system.
This book is a revision and expansion of a computer science classic. Every chapter has been thoroughly updated with Linux coverage.
Linux and the Unix Philosophy falls squarely between the "softer" texts on iterative software design and project management and the "how-to" technical texts. Thus far, no one has come out with a book that addresses this topic, either in the Unix space or the Linux space. Linux and the Unix Philosophy covers the same ground as the first edition, while it also presents bold new ideas about Linux and Open Source.
.Concise list of philosophy tenets makes it a handy quick reference
.Anecdotal examples personalize the book for the reader
.Conversational style makes it easy and joyful to read"

Dealing with system problems from user login failures to server crashes--is a critical part of a system administrator's job. A down system can cost a business thousands of dollars per minute. But there is little or no information available on how to troubleshoot and correct system problems; in most cases, these skills are learned in an ad-hoc manner, usually in the pressure-cooker environment of a crisis. This is the first book to address this lack of information.
The authors (both experienced Tru64 UNIX support engineer for Compaq) systematically present the techniques and tools needed to find and fix system problems. The first part of the book presents the general principles and techniques needed in system troubleshooting. These principles and techniques are useful not only for UNIX system administrators, but for anyone who needs to find and fix system problems. After this foundation, the authors describe troubleshooting tools used in the UNIX environment. The remainder of the book covers specific areas of the Tru64 UNIX operating system in detail: listing common problems, their causes, how to detect them, and how to correct them. Each chapter includes a "Before You Call Support" section that details the most important things to check and correct before it's necessary to call Compaq technical support. The authors also include decision trees to help the reader systematically isolate particular problem types.
. "Before You Call Tech Support" sections
.Tables and diagrams for quick access to precise data
.Decision trees to help choose the best way to troubleshoot a particular problem"

This book introduces a new level of abstraction that closes the gap between the textual specification of embedded systems and the executable model at the Electronic System Level (ESL). Readers will be enabled to operate at this new, Formal Specification Level (FSL), using models which not only allow significant verification tasks in this early stage of the design flow, but also can be extracted semi-automatically from the textual specification in an interactive manner. The authors explain how to use these verification tasks to check conceptual properties, e.g. whether requirements are in conflict, as well as dynamic behavior, in terms of execution traces.

Covering system architecture, implementation and testing, this work is written by authors who are widely experienced with cellular radio in general and with GSM in particular. It provides a structured overview to help make sense of the GSM specifications and surveys competing cellular systems such as NADC and CDMA. Practical testing applications are explored in depth and compared with similar techniques used with analogue cellular systems.

This book presents techniques necessary to predict cardiac arrhythmias, long before they occur, based on minimal ECG data. The authors describe the key information needed for automated ECG signal processing, including ECG signal pre-processing, feature extraction and classification. The adaptive and novel ECG processing techniques introduced in this book are highly effective and suitable for real-time implementation on ASICs.

This book discusses analysis, design and optimization techniques for streaming multiprocessor systems, while satisfying a given area, performance, and energy budget. The authors describe design flows for both application-specific and general purpose streaming systems. Coverage also includes the use of machine learning for thermal optimization at run-time, when an application is being executed. The design flow described in this book extends to thermal and energy optimization with multiple applications running sequentially and concurrently.

This book provides a comprehensive overview of both theoretical and pragmatic aspects of resource-allocation and scheduling in multiprocessor and multicore hard-real-time systems. The authors derive new, abstract models of real-time tasks that capture accurately the salient features of real application systems that are to be implemented on multiprocessor platforms, and identify rules for mapping application systems onto the most appropriate models. New run-time multiprocessor scheduling algorithms are presented, which are demonstrably better than those currently used, both in terms of run-time efficiency and tractability of off-line analysis. Readers will benefit from a new design and analysis framework for multiprocessor real-time systems, which will translate into a significantly enhanced ability to provide formally verified, safety-critical real-time systems at a significantly lower cost.

This thesis takes an empirical approach to understanding of the behavior and interactions between the two main components of reinforcement learning: the learning algorithm and the functional representation of learned knowledge. The author approaches these entities using design of experiments not commonly employed to study machine learning methods. The results outlined in this work provide insight as to what enables and what has an effect on successful reinforcement learning implementations so that this learning method can be applied to more challenging problems.

This book offers readers comprehensive coverage of security policy specification using new policy languages, implementation of security policies in Systems-on-Chip (SoC) designs - current industrial practice, as well as emerging approaches to architecting SoC security policies and security policy verification. The authors focus on a promising security architecture for implementing security policies, which satisfies the goals of flexibility, verification, and upgradability from the ground up, including a plug-and-play hardware block in which all policy implementations are enclosed. Using this architecture, they discuss the ramifications of designing SoC security policies, including effects on non-functional properties (power/performance), debug, validation, and upgrade. The authors also describe a systematic approach for "hardware patching", i.e., upgrading hardware implementations of security requirements safely, reliably, and securely in the field, meeting a critical need for diverse Internet of Things (IoT) devices. Provides comprehensive coverage of SoC security requirements, security policies, languages, and security architecture for current and emerging computing devices; Explodes myths and ambiguities in SoC security policy implementations, and provide a rigorous treatment of the subject; Demonstrates a rigorous, step-by-step approach to developing a diversity of SoC security policies; Introduces a rigorous, disciplined approach to "hardware patching", i.e., secure technique for updating hardware functionality of computing devices in-field; Includes discussion of current and emerging approaches for security policy verification.

This book provides a single-source reference to the state-of-the-art of high-level programming models and compilation tool-chains for embedded system platforms. The authors address challenges faced by programmers developing software to implement parallel applications in embedded systems, where very often they are forced to rewrite sequential programs into parallel software, taking into account all the low level features and peculiarities of the underlying platforms. Readers will benefit from these authors' approach, which takes into account both the application requirements and the platform specificities of various embedded systems from different industries. Parallel programming tool-chains are described that take as input parameters both the application and the platform model, then determine relevant transformations and mapping decisions on the concrete platform, minimizing user intervention and hiding the difficulties related to the correct and efficient use of memory hierarchy and low level code generation.

This book explores near-threshold computing (NTC), a design-space using techniques to run digital chips (processors) near the lowest possible voltage. Readers will be enabled with specific techniques to design chips that are extremely robust; tolerating variability and resilient against errors. Variability-aware voltage and frequency allocation schemes will be presented that will provide performance guarantees, when moving toward near-threshold manycore chips. * Provides an introduction to near-threshold computing, enabling reader with a variety of tools to face the challenges of the power/utilization wall; * Demonstrates how to design efficient voltage regulation, so that each region of the chip can operate at the most efficient voltage and frequency point; * Investigates how performance guarantees can be ensured when moving towards NTC manycores through variability-aware voltage and frequency allocation schemes.

This book explains for readers how 3D chip stacks promise to increase the level of on-chip integration, and to design new heterogeneous semiconductor devices that combine chips of different integration technologies (incl. sensors) in a single package of the smallest possible size. The authors focus on heterogeneous 3D integration, addressing some of the most important challenges in this emerging technology, including contactless, optics-based, and carbon-nanotube-based 3D integration, as well as signal-integrity and thermal management issues in copper-based 3D integration. Coverage also includes the 3D heterogeneous integration of power sources, photonic devices, and non-volatile memories based on new materials systems.

The development of computer technology, particularly the work of the Fifth Generation Computer Project of Japan, will have far-reaching international implications. The author explores the uses of the new generation computer and information systems now under development in Japan by identifying their application, assessing their impact on society, and envisioning the transition to the future.

* The ELS model of enterprise security is endorsed by the Secretary of the Air Force for Air Force computing systems and is a candidate for DoD systems under the Joint Information Environment Program. * The book is intended for enterprise IT architecture developers, application developers, and IT security professionals. * This is a unique approach to end-to-end security and fills a niche in the market.

This book introduces readers to the most advanced research results on Design for Manufacturability (DFM) with multiple patterning lithography (MPL) and electron beam lithography (EBL). The authors describe in detail a set of algorithms/methodologies to resolve issues in modern design for manufacturability problems with advanced lithography. Unlike books that discuss DFM from the product level or physical manufacturing level, this book describes DFM solutions from a circuit design level, such that most of the critical problems can be formulated and solved through combinatorial algorithms.

Networks-on-Chip: From Implementations to Programming Paradigms provides a thorough and bottom-up exploration of the whole NoC design space in a coherent and uniform fashion, from low-level router, buffer and topology implementations, to routing and flow control schemes, to co-optimizations of NoC and high-level programming paradigms.

This lecture is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture and Networks-on-Chip. It is also intended for practitioners in the industry in the area of microprocessor design, especially the many-core processor design with a network-on-chip. The graduates can learn many practical and theoretical lessons from this course, and also can be motivated to delve further into the ideas and designs proposed in this book. The industrial engineers can refer this book to make practicing tradeoffs as well. The graduates and engineers focus on off-chip network design can also refer this book for deadlock-free routing algorithm designs.
Provides thorough and insightful exploration of NoC design space. Description from low-level logic implementations to co-optimizations of high-level program paradigms and NoCs.The coherent and uniform description fashion offers the readers a clear, quick and efficient exploration of NoC design spaceCovers many novel and exciting research ideas, which encourage researchers to further delve into these topics.Presents both engineering and theoretical contributions. The detailed description of the router, buffer and topology implementations, comparisons and analysis are of high engineering value.

Architecting High Performing, Scalable and Available Enterprise Web Applications provides in-depth insights into techniques for achieving desired scalability, availability and performance quality goals for enterprise web applications. The book provides an integrated 360-degree view of achieving and maintaining these attributes through practical, proven patterns, novel models, best practices, performance strategies, and continuous improvement methodologies and case studies. The author shares his years of experience in application security, enterprise application testing, caching techniques, production operations and maintenance, and efficient project management techniques.

This book describes the state-of-the art of industrial and academic research in the architectural design of heterogeneous, multi/many-core processors. The authors describe methods and tools to enable next-generation embedded and high-performance heterogeneous processors to confront cost-effectively the inevitable variations by providing Dependable-Performance: correct functionality and timing guarantees throughout the expected lifetime of a platform under thermal, power, and energy constraints. Various aspects of the reliability problem are discussed, at both the circuit and architecture level, the intelligent selection of knobs and monitors in multicore platforms, and systematic design methodologies. The authors demonstrate how new techniques have been applied in real case studies from different applications domain and report on results and conclusions of those experiments. Enables readers to develop performance-dependable heterogeneous multi/many-core architectures Describes system software designs that support high performance dependability requirements Discusses and analyzes low level methodologies to tradeoff conflicting metrics, i.e. power, performance, reliability and thermal management Includes new application design guidelines to improve performance dependability