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Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design

Invasive Tightly Coupled Processor Arrays (Hardcover, 1st ed. 2016): Vahid Lari Invasive Tightly Coupled Processor Arrays (Hardcover, 1st ed. 2016)
Vahid Lari
R3,797 R3,471 Discovery Miles 34 710 Save R326 (9%) Ships in 12 - 19 working days

This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desired number of processing elements (PEs) or region within a TCPA exclusively for an application according to performance requirements. It not only presents models for implementing invasion strategies in hardware, but also proposes two distinct design flavors for dedicated hardware components to support invasion control on TCPAs.

Recent Advances in VLSI Design (Hardcover): Martin Limestone Recent Advances in VLSI Design (Hardcover)
Martin Limestone
R3,281 R2,965 Discovery Miles 29 650 Save R316 (10%) Ships in 10 - 15 working days
Design Technologies for Green and Sustainable Computing Systems (Hardcover, 2014 ed.): Partha Pratim Pande, Amlan Ganguly,... Design Technologies for Green and Sustainable Computing Systems (Hardcover, 2014 ed.)
Partha Pratim Pande, Amlan Ganguly, Krishnendu Chakrabarty
R2,890 Discovery Miles 28 900 Ships in 10 - 15 working days

This book provides a comprehensive guide to the design of sustainable and green computing systems (GSC). Coverage includes important breakthroughs in various aspects of GSC, including multi-core architectures, interconnection technology, data centers, high performance computing (HPC), and sensor networks. The authors address the challenges of power efficiency and sustainability in various contexts, including system design, computer architecture, programming languages, compilers and networking.

Domain Decomposition Methods in Science and Engineering XX (Hardcover, 2013 ed.): Randolph Bank, Michael Holst, Olof Widlund,... Domain Decomposition Methods in Science and Engineering XX (Hardcover, 2013 ed.)
Randolph Bank, Michael Holst, Olof Widlund, Jinchao Xu
R4,501 Discovery Miles 45 010 Ships in 10 - 15 working days

These are the proceedings of the 20th international conference on domain decomposition methods in science and engineering. Domain decomposition methods are iterative methods for solving the often very large linearor nonlinear systems of algebraic equations that arise when various problems in continuum mechanics are discretized using finite elements. They are designed for massively parallel computers and take the memory hierarchy of such systems in mind. This is essential for approaching peak floating point performance. There is an increasingly well developed theory whichis having a direct impact on the development and improvements of these algorithms.

Dynamic Reconfiguration in Real-Time Systems - Energy, Performance, and Thermal Perspectives (Hardcover, 2012): Weixun Wang,... Dynamic Reconfiguration in Real-Time Systems - Energy, Performance, and Thermal Perspectives (Hardcover, 2012)
Weixun Wang, Prabhat Mishra, Sanjay Ranka
R4,402 R3,545 Discovery Miles 35 450 Save R857 (19%) Ships in 12 - 19 working days

Given the widespread use of real-time multitasking systems, there are tremendous optimization opportunities if reconfigurable computing can be effectively incorporated while maintaining performance and other design constraints of typical applications. The focus of this book is to describe the dynamic reconfiguration techniques that can be safely used in real-time systems. This book provides comprehensive approaches by considering synergistic effects of computation, communication as well as storage together to significantly improve overall performance, power, energy and temperature."

System Verilog Assertions and Functional Coverage - Guide to Language, Methodology and Applications (Hardcover, 3rd ed. 2020):... System Verilog Assertions and Functional Coverage - Guide to Language, Methodology and Applications (Hardcover, 3rd ed. 2020)
Ashok B. Mehta
R3,931 Discovery Miles 39 310 Ships in 12 - 19 working days

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and Functional Coverage. Readers will benefit from the step-by-step approach to learning language and methodology nuances of both SystemVerilog Assertions and Functional Coverage, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of ASIC/SoC/CPU and FPGA design and Verification, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification and exhaustive coverage models for functional coverage, thereby drastically reducing their time to design, debug and cover. This updated third edition addresses the latest functional set released in IEEE-1800 (2012) LRM, including numerous additional operators and features. Additionally, many of the Concurrent Assertions/Operators explanations are enhanced, with the addition of more examples and figures. * Covers in its entirety the latest IEEE-1800 2012 LRM syntax and semantics; * Covers both SystemVerilog Assertions and SystemVerilog Functional Coverage languages and methodologies; * Provides practical applications of the what, how and why of Assertion Based Verification and Functional Coverage methodologies; * Explains each concept in a step-by-step fashion and applies it to a practical real life example; * Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book.

Exploiting Linked Data and Knowledge Graphs in Large Organisations (Hardcover, 1st ed. 2017): Jeff Z. Pan, Guido Vetere, Jose... Exploiting Linked Data and Knowledge Graphs in Large Organisations (Hardcover, 1st ed. 2017)
Jeff Z. Pan, Guido Vetere, Jose Manuel Gomez- Perez, Honghan Wu
R5,311 Discovery Miles 53 110 Ships in 12 - 19 working days

This book addresses the topic of exploiting enterprise-linked data with a particular focus on knowledge construction and accessibility within enterprises. It identifies the gaps between the requirements of enterprise knowledge consumption and "standard" data consuming technologies by analysing real-world use cases, and proposes the enterprise knowledge graph to fill such gaps. It provides concrete guidelines for effectively deploying linked-data graphs within and across business organizations. It is divided into three parts, focusing on the key technologies for constructing, understanding and employing knowledge graphs. Part 1 introduces basic background information and technologies, and presents a simple architecture to elucidate the main phases and tasks required during the lifecycle of knowledge graphs. Part 2 focuses on technical aspects; it starts with state-of-the art knowledge-graph construction approaches, and then discusses exploration and exploitation techniques as well as advanced question-answering topics concerning knowledge graphs. Lastly, Part 3 demonstrates examples of successful knowledge graph applications in the media industry, healthcare and cultural heritage, and offers conclusions and future visions.

Embedded Systems Design for High-Speed Data Acquisition and Control (Hardcover, 2015 ed.): Maurizio Di Paolo Emilio Embedded Systems Design for High-Speed Data Acquisition and Control (Hardcover, 2015 ed.)
Maurizio Di Paolo Emilio
R4,162 Discovery Miles 41 620 Ships in 12 - 19 working days

This book serves as a practical guide for practicing engineers who need to design embedded systems for high-speed data acquisition and control systems. A minimum amount of theory is presented, along with a review of analog and digital electronics, followed by detailed explanations of essential topics in hardware design and software development. The discussion of hardware focuses on microcontroller design (ARM microcontrollers and FPGAs), techniques of embedded design, high speed data acquisition (DAQ) and control systems. Coverage of software development includes main programming techniques, culminating in the study of real-time operating systems. All concepts are introduced in a manner to be highly-accessible to practicing engineers and lead to the practical implementation of an embedded board that can be used in various industrial fields as a control system and high speed data acquisition system.

More than Moore Technologies for Next Generation Computer Design (Hardcover, 2015 ed.): Rasit O. Topaloglu More than Moore Technologies for Next Generation Computer Design (Hardcover, 2015 ed.)
Rasit O. Topaloglu
R3,845 R3,563 Discovery Miles 35 630 Save R282 (7%) Ships in 12 - 19 working days

This book provides a comprehensive overview of key technologies being used to address challenges raised by continued device scaling and the extending gap between memory and central processing unit performance. Authors discuss in detail what are known commonly as "More than Moore" (MtM), technologies, which add value to devices by incorporating functionalities that do not necessarily scale according to "Moore's Law". Coverage focuses on three key technologies needed for efficient power management and cost per performance: novel memories, 3D integration and photonic on-chip interconnect.

Towards Next Generation Grids - Proceedings of the CoreGRID Symposium 2007 (Hardcover, 2007 ed.): Thierry Priol, Marco Vanneschi Towards Next Generation Grids - Proceedings of the CoreGRID Symposium 2007 (Hardcover, 2007 ed.)
Thierry Priol, Marco Vanneschi
R4,388 Discovery Miles 43 880 Ships in 10 - 15 working days

This book is the fifth volume of the CoreGRID series. Organized jointly with the Euro-Par 2007 conference, The CoreGRID Symposium intends to become the premiere European event on Grid Computing. The aim of this symposium is to strengthen and advance scientific and technological excellence in the area of Grid and Peer-to-Peer Computing. The book includes all aspects of Grid Computing including service infrastructure. It is designed for a professional audience composed of researchers and practitioners in industry. This volume is also suitable for advanced-level students in computer science.

Processor Description Languages, Volume 1 (Hardcover): Prabhat Mishra, Nikil Dutt Processor Description Languages, Volume 1 (Hardcover)
Prabhat Mishra, Nikil Dutt
R1,941 Discovery Miles 19 410 Ships in 12 - 19 working days

Efficient design of embedded processors plays a critical role in embedded systems design. Processor description languages and their associated specification, exploration and rapid prototyping methodologies are used to find the best possible design for a given set of applications under various design constraints, such as area, power and performance.
This book is the first, comprehensive survey of modern architecture description languages and will be an invaluable reference for embedded system architects, designers, developers, and validation engineers. Readers will see that the use of particular architecture description languages will lead to productivity gains in designing particular (application-specific) types of embedded processors.
* Comprehensive coverage of all modern architecture description languages... use the right ADL to design your processor to fit your application;
* Most up-to-date information available about each architecture description language from the developers...save time chasing down reliable documentation;
* Describes how each architecture desccription language enables key design automation tasks, such as simulation, synthesis and testing...fit the ADL to your design cycle;

Multimedia Multiprocessor Systems - Analysis, Design and Management (Hardcover, 2010): Akash Kumar, Henk Corporaal, Bart... Multimedia Multiprocessor Systems - Analysis, Design and Management (Hardcover, 2010)
Akash Kumar, Henk Corporaal, Bart Mesman, Yajun Ha
R2,971 Discovery Miles 29 710 Ships in 10 - 15 working days

Modern multimedia systems are becoming increasingly multiprocessor and heterogeneous to match the high performance and low power demands placed on them by the large number of applications. The concurrent execution of these applications causes interference and unpredictability in the performance of these systems. In Multimedia Multiprocessor Systems, an analysis mechanism is presented to accurately predict the performance of multiple applications executing concurrently. With high consumer demand the time-to-market has become significantly lower. To cope with the complexity in designing such systems, an automated design-flow is needed that can generate systems from a high-level architectural description such that they are not error-prone and consume less time. Such a design methodology is presented for multiple use-cases -- combinations of active applications. A resource manager is also presented to manage the various resources in the system, and to achieve the goals of performance prediction, admission control and budget enforcement.

Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications (Hardcover, 2010 ed.): Marco Platzner,... Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications (Hardcover, 2010 ed.)
Marco Platzner, Norbert Wehn
R3,144 Discovery Miles 31 440 Ships in 10 - 15 working days

Dynamically Reconfigurable Systems is the first ever to focus on the emerging field of Dynamically Reconfigurable Computing Systems. While programmable logic and design-time configurability are well elaborated and covered by various texts, this book presents a unique overview over the state of the art and recent results for dynamic and run-time reconfigurable computing systems.

Reconfigurable hardware is not only of utmost importance for large manufacturers and vendors of microelectronic devices and systems, but also a very attractive technology for smaller and medium-sized companies. Hence, Dynamically Reconfigurable Systems also addresses researchers and engineers actively working in the field and provides them with information on the newest developments and trends in dynamic and run-time reconfigurable systems.

Architecture Design for Soft Errors (Hardcover): Shubu Mukherjee Architecture Design for Soft Errors (Hardcover)
Shubu Mukherjee
R1,867 Discovery Miles 18 670 Ships in 12 - 19 working days

This book provides a comprehensive description of the architetural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp of the broader problem deffinition and solution space, this book also delves into the physics of soft errors and reviews current circuit and software mitigation techniques.
TABLE OF CONTENTS
Chapter 1: Introduction
Chapter 2: Device- and Circuit-Level Modeling, Measurement, and Mitigation
Chapter 3: Architectural Vulnerability Analysis
Chapter 4: Advanced Architectural Vulnerability Analysis
Chapter 5: Error Coding Techniques
Chapter 6: Fault Detection via Redundant Execution
Chapter 7: Hardware Error Recovery
Chapter 8: Software Detection and Recovery
* Helps readers build-in fault tolerance to the billions of microchips produced each year, all of which are subject to soft errors
* Shows readers how to quantify their soft error reliability
* Provides state-of-the-art techniques to protect against soft errors

High Quality Test Pattern Generation and Boolean Satisfiability (Hardcover, 2012): Stephan Eggersgluss, Rolf Drechsler High Quality Test Pattern Generation and Boolean Satisfiability (Hardcover, 2012)
Stephan Eggersgluss, Rolf Drechsler
R2,880 Discovery Miles 28 800 Ships in 10 - 15 working days

This book provides an overview of automatic test pattern generation (ATPG) and introduces novel techniques to complement classical ATPG, based on Boolean Satisfiability (SAT). A fast and highly fault efficient SAT-based ATPG framework is presented which is also able to generate high-quality delay tests such as robust path delay tests, as well as tests with long propagation paths to detect small delay defects.

The aim of the techniques and methodologies presented in this book is to improve SAT-based ATPG, in order to make it applicable in industrial practice. Readers will learn to improve the performance and robustness of the overall test generation process, so that the ATPG algorithm reliably will generate test patterns for most targeted faults in acceptable run time to meet the high fault coverage demands of industry. The techniques and improvements presented in this book provide the following advantages:

Provides a comprehensive introduction to test generation and Boolean Satisfiability (SAT);Describes a highly fault efficient SAT-based ATPG framework; Introduces circuit-oriented SAT solving techniques, which make use of structural information and are able to accelerate the search process significantly;Provides SAT formulations for the prevalent delay faults models, in addition to the classical stuck-at fault model;Includes an industrial perspective on the state-of-the-art in the testing, along with SAT; two topics typically distinguished from each other.

"

Fundamental Problems in Computing - Essays in Honor of Professor Daniel J. Rosenkrantz (Hardcover, 2009 ed.): Sekharipuram S.... Fundamental Problems in Computing - Essays in Honor of Professor Daniel J. Rosenkrantz (Hardcover, 2009 ed.)
Sekharipuram S. Ravi, Sandeep Kumar Shukla
R3,187 Discovery Miles 31 870 Ships in 10 - 15 working days

Fundamental Problems in Computing is in honor of Professor Daniel J. Rosenkrantz, a distinguished researcher in Computer Science. Professor Rosenkrantz has made seminal contributions to many subareas of Computer Science including formal languages and compilers, automata theory, algorithms, database systems, very large scale integrated systems, fault-tolerant computing and discrete dynamical systems. For many years, Professor Rosenkrantz served as the Editor-in-Chief of the Journal of the Association for Computing Machinery (JACM), a very prestigious archival journal in Computer Science. His contributions to Computer Science have earned him many awards including the Fellowship from ACM and the ACM SIGMOD Contributions Award.

Constraining Designs for Synthesis and Timing Analysis - A Practical Guide to Synopsys Design Constraints (SDC) (Hardcover,... Constraining Designs for Synthesis and Timing Analysis - A Practical Guide to Synopsys Design Constraints (SDC) (Hardcover, 2013 ed.)
Sridhar Gangadharan, Sanjay Churiwala
R4,249 Discovery Miles 42 490 Ships in 12 - 19 working days

This volume gives the latest developments in on the mechanisms of cancer cell resistance to apoptotic stimuli, which eventually result in cancer progression and metastasis. One of the main challenges in cancer research is to develop new therapies to combat resistant tumors. The development of new effective therapies will be dependent on delineating the biochemical, molecular, and genetic mechanisms that regulate tumor cell resistance to cytotoxic drug-induced apoptosis. These mechanisms should reveal gene products that directly regulate resistance in order to develop new drugs that target these resistance factors and such new drugs may either be selective or common to various cancers. If successful, new drugs may not be toxic and may be used effectively in combination with subtoxic conventional drugs to achieve synergy and to reverse tumor cell resistance. The research developments presented in this book can be translated to produce better clinical responses to resistant tumors.

Reconfigurable Computing, Volume 1 - The Theory and Practice of FPGA-Based Computation (Hardcover): Scott Hauck, Andre Dehon Reconfigurable Computing, Volume 1 - The Theory and Practice of FPGA-Based Computation (Hardcover)
Scott Hauck, Andre Dehon
R2,174 Discovery Miles 21 740 Ships in 12 - 19 working days

The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.
- Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
- Views of FPGA programming beyond Verilog/VHDL
- Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways

An ASIC Low Power Primer - Analysis, Techniques and Specification (Hardcover, 2013 ed.): Rakesh Chadha, J. Bhasker An ASIC Low Power Primer - Analysis, Techniques and Specification (Hardcover, 2013 ed.)
Rakesh Chadha, J. Bhasker
R4,222 Discovery Miles 42 220 Ships in 12 - 19 working days

This book provides an invaluable primer on the techniques utilized in the design of low power digital semiconductor devices. Readers will benefit from the hands-on approach which starts form the ground-up, explaining with basic examples what power is, how it is measured and how it impacts on the design process of application-specific integrated circuits (ASICs). The authors use both the Unified Power Format (UPF) and Common Power Format (CPF) to describe in detail the power intent for an ASIC and then guide readers through a variety of architectural and implementation techniques that will help meet the power intent. From analyzing system power consumption, to techniques that can be employed in a low power design, to a detailed description of two alternate standards for capturing the power directives at various phases of the design, this book is filled with information that will give ASIC designers a competitive edge in low-power design.

Heterogeneous Memory Organizations in Embedded Systems - Placement of Dynamic Data Objects (Hardcover, 1st ed. 2020): Miguel... Heterogeneous Memory Organizations in Embedded Systems - Placement of Dynamic Data Objects (Hardcover, 1st ed. 2020)
Miguel Peon Quiros, Francky Catthoor, Jose Manuel Mendias Cuadros
R1,530 Discovery Miles 15 300 Ships in 10 - 15 working days

This book defines and explores the problem of placing the instances of dynamic data types on the components of the heterogeneous memory organization of an embedded system, with the final goal of reducing energy consumption and improving performance. It is one of the first to cover the problem of placement for dynamic data objects on embedded systems with heterogeneous memory architectures, presenting a complete methodology that can be easily adapted to real cases and work flows. The authors discuss how to improve system performance and energy consumption simultaneously. Discusses the problem of placement for dynamic data objects on embedded systems with heterogeneous memory architectures; Presents a complete methodology that can be adapted easily to real cases and work flows; Offers hints on how to improve system performance and energy consumption simultaneously.

Learning from VLSI Design Experience (Hardcover, 1st ed. 2019): Weng Fook Lee Learning from VLSI Design Experience (Hardcover, 1st ed. 2019)
Weng Fook Lee
R3,627 Discovery Miles 36 270 Ships in 10 - 15 working days

This book shares with readers practical design knowledge gained from the author's 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds.

Self-Organization in Embedded Real-Time Systems (Hardcover, 2012): M. Teresa Higuera-Toledano, Uwe Brinkschulte, Achim Rettberg Self-Organization in Embedded Real-Time Systems (Hardcover, 2012)
M. Teresa Higuera-Toledano, Uwe Brinkschulte, Achim Rettberg
R3,522 Discovery Miles 35 220 Ships in 12 - 19 working days

This book describes the emerging field of self-organizing, multicore, distributed and real-time embedded systems. Self organization of both hardware and software can be a key technique to handle the growing complexity of modern computing systems. Distributed systems running hundreds of tasks on dozens of processors, each equipped with multiple cores, requires self organization principles to ensure efficient and reliable operation. This book addresses various, so-called Self X features such as self-configuration, self optimization, self adaptation, self healing and self protection."

More-than-Moore 2.5D and 3D SiP Integration (Hardcover, 1st ed. 2017): Riko Radojcic More-than-Moore 2.5D and 3D SiP Integration (Hardcover, 1st ed. 2017)
Riko Radojcic
R4,114 Discovery Miles 41 140 Ships in 10 - 15 working days

This book presents a realistic and a holistic review of the microelectronic and semiconductor technology options in the post Moore's Law regime. Technical tradeoffs, from architecture down to manufacturing processes, associated with the 2.5D and 3D integration technologies, as well as the business and product management considerations encountered when faced by disruptive technology options, are presented. Coverage includes a discussion of Integrated Device Manufacturer (IDM) vs Fabless, vs Foundry, and Outsourced Assembly and Test (OSAT) barriers to implementation of disruptive technology options. This book is a must-read for any IC product team that is considering getting off the Moore's Law track, and leveraging some of the More-than-Moore technology options for their next microelectronic product.

Grid Computing Security (Hardcover, 2007 ed.): Anirban Chakrabarti Grid Computing Security (Hardcover, 2007 ed.)
Anirban Chakrabarti
R1,567 Discovery Miles 15 670 Ships in 10 - 15 working days

Based on research and industry experience, this book structures the issues pertaining to grid computing security into three main categories: architecture-related, infrastructure-related, and management-related issues. It discusses all three categories in detail, presents existing solutions, standards, and products, and pinpoints their shortcomings and open questions. Together with a brief introduction into grid computing in general and underlying security technologies, this book offers the first concise and detailed introduction to this important area, targeting professionals in the grid industry as well as students.

Correct-by-Construction Approaches for SoC Design (Hardcover, 2014 ed.): Roopak Sinha, Parthasarathi Roop, Samik Basu Correct-by-Construction Approaches for SoC Design (Hardcover, 2014 ed.)
Roopak Sinha, Parthasarathi Roop, Samik Basu
R4,056 R3,486 Discovery Miles 34 860 Save R570 (14%) Ships in 12 - 19 working days

This book describes an approach for designing Systems-on-Chip such that the system meets precise mathematical requirements. The methodologies presented enable embedded systems designers to reuse intellectual property (IP) blocks from existing designs in an efficient, reliable manner, automatically generating correct SoCs from multiple, possibly mismatching, components.

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